; *** (c) 1993 COPYRIGHT 1993 by J. V. POLL *** ; ;TBT799,800 01-21-93 01-22-92 01-23-92 Call Group Name review/edit works, CG ; Code too! ;TBT798 01-21-93 Call Group Name review/edit works, CG Code review only is ; implemented. ;TBT796,7 01-17-93 Implement CALL Group data edit/entry. ; 01-20-93 Review w/blinking cursor implemented. The 0600H limit has ; been exceeded. Down below 0600H limit now but Char Inc for Call Group ; name doesn't work. ;TBT793,4,5 01-16-93 Cont 790's plans. Implemented ADDTOHL subroutine. OK ; The Call Group increment and store is working, Implemented BLINK ; and UNBLINK subroutines. ; Next up is the Hex data entry for call groups. ; Ought to add Hot Keys for: ; 1) Lock-out function in TRAK mode ; 2) Call Group ID ; 3) Add a review and UNLock mode. ;TBT791,2 01-16-93 Cont 790's plans. Got 16 CG List to work. ;TBT790 01-16-93 Plans: Link the DATA ENter Routine to Call Group list, add ; code to copy initial CG List RH, LH and CHL from ROM into RAM, ; add Call Group MaSK entry. ; This version: Re-arranged ROM/RAM CGLIST data preparing for above. OK! ;TBT789 01-13-93 Added more OSW ADDR codes to ignore. ;TBT788 01-11-93 Replaced McKinney Setup Channel list w/Plano's. OK! ;TBT787 01-10-93 This version uses a lookup table in ROM for the PLANO system. ; Got the C0ONBGD code working again. OK. ; Two techniques can be implemented for tracking on the Plano system: ; 1) A correction factor added or subtracted from the data, knowing ; what are the data or frequency codes. ; 2) A look-up table. The look-up table would require the entry of ; the freq code as used by the system along with the frequency ; (or offset) as input from the scanner. ; ;TBT786 01-09-93 Incorp OSW Freq/Data inspection. Worked! ;TBT785 01-09-93 Moved variables around, gained some additional space. ;TBT784 01-09-93 Shorten OSW addrs search loop. The order of the LH (MSH) ; of the OSW addr in CGLISTxx had to be reversed since BC is being ; added to IY for the index and the count in BC is decremented. ;TBT783 01-08-93 Added Channel label output to display from list. OK! ;TBT782 01-08-93 Optimize code used in OSW address search. Working! ; The DATA entry routine should might be changed to point to the buffer ; to be changed. ; Incorporate an OSW MASK for address bit screening. Not this ver. ; Incorporate OSW Data shift function for the PLANO system. Not this ver. ;TBT781 01-07-93 Write new CALL GROUP scan code. Basic code is working using ; CPIR inst. Need to implement DATA to RAM routine now. ;TBT780 01-05-93 There is a delay in RSYN select due to an extra step that ; looks for the ENTER Key. Re-arranged menu selection and incorporate ; menu software. OK ; ; Menu structure: ; Start ; | ; ---------------------------------------------------- ; | | | | ; | | | | ; *Track (TRAK) Scan Setup (RST) *Reset (RST) ; | ; -------------------------- ; | | | ; Mask Call Freq (RSYN) ; Group ; Rules: Enter Key actuates lower member ; Mode Key selects previous mode * Done ; ;TBT779 01-04-93 01-03-93 Change menu code. Got it to work. ;TBT778 01-03-93 Polish up comments. Perhaps consolidate, revise DATA subs. OK! ;TBT777 01-02-93 Keyboard data entry routine. WOrked OK. ;TBT776 01-02-93 Packed RAM more closely, fixed Syn Shift bit problem. ;TBT774,5 01-02-93 Incorp'd Plano 01D0 code track - seems to be an error in ; calculating the destination frequency - the problem seems to be with ; the /Syn shift bit. There was - fixed now. Recommend changing to store ; Syn Shift bit in native mode and invert it in the Syn driver output ; routine. ;TBT770,1,2,3 01-01-93 Re-arrange everything for the purpose of getting code we ; need modified into the lower memory block. Worked OK!! ; Tried tracking Plano: didn't seem to properly compute destination ; Voice Channel. Turns out that the data structure is different here. ;TBT765,6 12-27-92 12-30-92 Coded back in McKinney PD codes. OK! ; Should also work on a simple keyboard data entry routine for Call ; Group and mask entry before further work is done in upper memory to ; make use of it. A means to edit/review should be worked up. ; Corrected design error: Added resetting of PRVDATGD flag in HSIRSU. ; Turns out that the program was bouncing between HS and LS as the ; the previous data and counts were not cleared when a matching addr ; was found. ;TBT764 12-27-93 Incorp'd max pointer. Reset during entry of base frequency. ; It looked like the return to the Setup Channel wasn't being made, ; and a search through the list was being performed. ; Next, develop scan mode - suggestions: ; 1) roll through setup channel list, stopping on an active channel ; use either carrier detect or LS detect to qualify as active CH ; or 2) Pick off legit codes on a first come-first serve basis from SC and ; track. ; ;TBT763 12-27-92 OK. Incorp'd reading of base frequency. This is accomplished ; by programming the scanner for +10 MHz above the base frequency into ; location F0. For Plano, the base freq is 848.000 MHz (+ 10 = 858.000) ; McKinney, the base freq is 851.025 MHz (+ 10 = 861.025) ; The max pointer still needs to be put in to allow scanning for Setup ; CHannels beyond the list of just five. ; ;TBT762P 12-27-92 Incorp'd Plano codes: the base freq seems to be 847.950 ; Plan: 1) Change direct use from 82CE to use SYNBASEL/H variables instead. ; 2) Incorp ability to read in the base freq. Some of these base freqs ; will have to be offset by a fixed amount like 10 MHz since nothing ; below 850 MHz can be programmed into the BC760XLT. ; ;TBT760,1,2 11-18-92 12-26-92 Read SYNFSHFT from RAM - Ran OK. This version ; can be programmed to work from strictly from the STCH list in ; RAM. ;TBT758,9 11-16-92 11-17-92 Incorp'd read Syn data into RAM in RDS routine. ; Must still incorp reading of shift bit into Syn output rou. ; Still more work to do, almost works-very close. ;TBT757 11-15-92 Incorp'd RST mode in old 'READ' position. ;TBT756 11-15-92 Incorp freq list for scanning, havn't set to pgm syn from ; it yet, though - still have to work out details of the format ; of the data since the old list contained only the offset ; from the base frequency. Options are to subtact the base freq ; from the read freq in the Synth Data read routine and then ; store it in RAM. ;TBT755 11-14-92 Enabled ints in CT 1 Keyboard int service routine to solve ; a problem wherein occasionally when reading Synth data ; during the RSD Wait Loop data was in error - runs OK. ;TBT754 11-14-92 Mode proposals: ; Freq entry Mode: Frequency scan list (primarily for Setup Channel observing. ; The code should read frequency f/scanner data into a scan list. ; For debug purposes, initially copy from PROM into RAM scan list. ; ; Band limit scan Mode: ID'ing Mot 3.6KHz systems ; ; ;TBT752,3 11-14-92 Wrote Synth freq display mode read mode - OK. ;TBT750,1 11-14-92 Incorp'd RDMDSWDAT sub to clr read Mode Sw data. ;TBT749 11-14-92 Bouncing between MODE TRAK and READ dummy routines w/KYB ; works OK. Proposed that depression of MODE bring back control ; to MODE routine, L-R arrows then cycle through modes: ; TRAK READ etc. ;TBT748 11-11-92 Added ASCII character file, added clring of MDSWDAT3 and ; register exchanges to solve bouncing problem. ;TBT746,7 11-9-92 Got Mode and TRAKMD loops bouncing back and forth. ;TBT745 11-8-92 Solved problem with CTC 0 ints during CT 1 Key board timer ; operation - PIO A int had not been disabled and CT 0 is ; written to within the PIO A Int routine re-activating it. ;TBT744 11-8-92 CT1KTI Routine returns data in MDSWDAT3 after key clears. ;TBT743 11-7-92 11-8-92 Implementing timed keyboard interrupt using CTC 1. ; A short dummy int routine was needed for HS CTC 0 service ; after going into MODE 1 code in order to flush out a pending ; interrupt. Sw Data appears as: 0000 LMRE Left Right ; <-- --> Top ; Mode Ent Bot ;TBT742 11-7-92 Jump into and out of Track code via switching - OK. ;TBT741 11-7-92 Moved CT0HSTS High Speed timing service after Sync Qualifying, ; Ran OK - jitter seems to be down, HS sampling point looks ; centered. Adjusted counts to center CT0HSIR. OK ;TBT740 11-7-92 Incorp'd simple read mode switch in HS Sync routine - OK. ; Reads lower left switch. ;TBT738,9 10-30-92,11-2-92 Implemented use of HL pointer into 1st part of ; CT0HSI routine - RAN OK. ;TBT737 10-29-93 Back on 386DX33, finished indexed table for Sync period ops, ; seemed to run OK! ;TBT736 10-28-92 10-29-92 Spruce up comments. ;TBT735,A 10-27-92 10:07PM Version Ran OK! ;TBT734 10-22-92 As it turns out, we are at the limit as to what can be ; processed in the HS Sync period. Adding in the scanning ; of the keyboard puts us over the edge. ;TBT733 10-22-92 Save Mute line status in OLDSDATA. ;TBT732 10-21-92 Debug - found that MUTE is not preserved in OLDSDATA. ;TBT730,1 10-20-92 10-21-92 Write/test the Keyboard scan code. ;TBT729 10-19-92 Comment cleanup - next needed is keyboard scan code - 2 x 3 ; matrix (two out SW OUT 0 and 1 and three in SW IN 0, 1, 2). ;TBT728 10-14-92 Incorp read of Shift bit - this signal requires pull down ; resistor on the pin from the radio. Works OK w/resistor. ;TBT726,7 10-11-92 10-14-92 Writing SYN read serial-to-parallel code - OK! ;TBT724,5 10-9-92 10-11-92 PIO-A responds to SYN Clk and CTC 3 responds to EN!! ;TBT722,3 10-05-92 10-7-92 Incorp CTC 3 for detection of positive going ENable ; line. ;TBT721 10-03-92 Working on ints - see * Note further below. Kinda working. ;TBT718,19,20 10-03-92 Writing actual mode change code and Serial data from Rcvr ; code - RAN! ;TBT717 10-02-92 Begin to incorp mode reading code ;TBT716 10-02-92 Comments yet ... ;TBT715 10-01-92 Make PIO A Int setup callable - didn't, just looked into it. ;TBT714 10-01-92 Added to comments. ;TBT711,2,3 9-29-92 9-30-92 10-1-92 Edited on XT and 386SX. Ran OK!! ;TBT710 9-29-92 Shifted upper program to start at ORG'd at calc'd addrs. OK! ;TBT704 9-27-92 Continued work started in TBT701 ... 16:55 RAN OK ;TBT703 9-27-92 Continued work started in TBT701 ... RAN OK ;TBT702 9-27-92 Continued work started in TBT701 ... RAN OK ;TBT701 9-26-92 Comment improvements, changes in varaiable and subroutine names ;TBT700 9-24-92 Copied from 641C, re-arrange, ORG at new addresses: *OK!* ; PROM 1 PROM 2 RAM DISPLAY ; 000-7FF 800-FFF 1000-17FF 2000-2007 ;TBT641C 9-20-92 Added S - N output when losing HS Sync, also added display ; setup 83 Hex - required when powering up. ;TBT641B 9-19-92 Changed to blank Left 3 digits in HS SYNC mode - worked! ;TBT641A 9-19-92 Added McKinney PD ;TBT641 9-19-92 Added code to output APD_ FPD_ with xxxS when returning to ; setup channel - worked. ;TBT640 9-19-92 Added test output to 4-char ASCII display - worked! ;TBT637 8-28-92 Changed McKPD to ?? 25 hex ;TBT636 8-22-92 Changed PIO A HS PLL CTC 0 re-load values. ;TBT633,4 8-21-92 In CT0LS had SYNFND instead of lsSYNFND - fixed now. ;TBT632 Add more codes to track ;TBT631 8-18-92 Looks like a simple error in ls and HS Sync qualifying. Also had ; badly implemeted Mute code, replaced in this generation. ;TBT629A 8-17-92 Added simple Mute code - worked - one every second or so it ; looks like the receiver goes back to sample the Setup Channel. ; ;TBT629 8-17-92 Incorp Low Speed Sync qualifying. ;TBT628 8-16-92 Incorp passing of serial data to syn - trunk track - ; seems to work! chgd 20 to 30 in HS SYNC not present qualifying. ; ***---> Need to add LS SYNC present/not present qualifying like HS. ; ***---> Need to add MUTE Line control, too. ;TBT627 8-16-92 Incorp 1st try at SC search loop - worked after debug. ;TBT626 8-16-92 Re-arrange calls to set up greq synthesizer in scanner. ;TBT625 8-16-92 Re-organizing to allow INT vectors to be programmable - HS ; worked OK - try LS - worked OK after debugging. ;TBT624 8-16-92 Make CTC setup for LS and HS callable subroutines - worked OK. ;TBT623 8-16-92 Incorp Setup Channel Frequency list - worked OK. ;TBT622 8-15-92 Move wait loop code ahead of SYN programming code. ; 1) Made SYNSERBC1 CALLable - worked OK, now try putting DI/EI's ; into WAITLP - worked OK, now add together offset + base freqs ; for programming - worked OK. ;TBT620,1 8-15-92 Wrote HS SYNC qualifying code - works! Set vals to 8/48. ; Also set up HSSYNAB flag. ;TBT619 8-11-92 Working on getting switch over logic incorporated. ; Will have to incorporate Sync loss logic in HS Sync ; and LS Sync int routines. ; Also change some Variable names such as SYNPCT to SYNPB84CT ; and lsSYNPCT to lsSYPB21C. ; ;TBT618 8-9-92 Corrected a single bit error in OSWIBT - Chan 3 was picking ; up an extra bit. Screening and ID of Call groups begun - working OK. ;TBT617 8-9-92 Ignore ceratain words Incorp'd - worked OK. ;TBT616 8-9-92 Trapping for just certain OSW data - works! ;TBT615 8-9-92 Selected High Speed data operations - still works!. ;TBT614 8-9-92 Changed Sync period pgm action locations. worked OK w/Dis Seq. ;TBT613 8-8-92 Adding code to DiS SEQ int routine to qualify Dis seq. OK!! ;TBT611,2 8-8-92 Adding comments to Disconnect Sequence int routine. ;TBT610 8-1-92 LS Data lock, Disconnect sequence and CTC 2 SCF clock look OK. ;TBT609 8-1-92 Minor HS changes, also wrote LS SCF code for upcoming test. OK! ;TBT607,8 7-31-92 Incorp SYN Freq Shift bit output, enable HS data acquisition. ;TBT606 7-19-92 Program CTC2 for 250 KHz clock for SCF - worked OK! ;TBT605 7-19-92 Found out CLK and EN were swapped in documentation!!! ; Serial data output Works OK!!! ;TBT604 7-16-92 Set up the data 5 uS before clock pulses low. ; ;TBT601,2,3 7-12-92 7-16-92 Incorp serial data Output for BC760XLT - first ever ; use of a callable subroutine - worked OK! ;TBT600 7-12-92 Some comment cleanup ... ;TBT543 Made switch over to HS data aquisition to assure it still works - OK! ;TBT542 LS sampling occurs approx .25 mS after ideal - try to correct. Ran OK ;TBT541 Polish up Disconnect code - Ran OK, occasional false data detected. ;TBT540 Status: 1) HS Clock, Sync, and data aquisition code works ; Phase lock code could use a little faster aquisition, ; especially in the "dead-band" range where CNT84 count rolls ; over. ; 2) LS Clock and Sync code works. ; ; Plans: 1) Incorp LS Data aquistion - basically a copy of HS code ; 2) Incorp LS Disconnect Byte recognition - probably use another ; CTC set in reference to the phase-locked CTC ; ; Imp. Results: 1) Disconnect detect using services from CTC 1 are working. ; ; ;TBT535 Corr err in PIO LS - forgot to restore regs and ADDs were incorr. ; Runs OK now - Pull in is pretty quick. ;TBT534 LS PIO routine runs OK - PIO is triggering on Negative edge, however, ; and this is affecting Disconnect Word phase lock. ;TBT533 Going to add LS PIO routine. ;TBT530,1,2 Incorp LS data read, lock - 531: Ratiometric count scheme works OK. ; Sync recognition works OK - must also implement PIO phase lock code. ;TBT523,4 Minor re-arranging, add/chg comments. RAN OK. ;TBT522 Minor Touch up - ran OK. ;TBT520,1 Work on Sync - Looks pretty good now! ;TBT513 Change output data format - ; 940 - High byte, 941 - Low byte, 942 - Call Type and high two Freq/ ; Data bits, 943 - Low byte Freq/Data bits ;TBT512 Was error in OSWIBT- must place incoming data into MSB first. Also ; dummied all unused incoming bits to SPARE (11xx xxxx). Ran OK after ; fixes!! Set Logic Analyzer to trap 094xH and /WR to view trunked data: ; 940 - High byte, 941 - Low byte, 942 - Call Type, 943 - high two Freq/ ; Data bits, 944 - Low byte Freq/Data bits ;TBT511 Looks like we have parallel data being written to memory ... observed ; on Logic Analyser - used as Output Display device. ;TBT510 Change OSWIBT table: re-position Axx, T, C bits in memory, Clr SYNC ; Pat Cnt in CT0IN122. ;TBT502,3 Re-code Sync code using new algorithym. Runs OK after 1 corr!!! ;TBT500,1 F/TBT443, change to 4 MHz clock. Looks OK w/o data recon code enabled. ;TBT442 Incorp new Sync recognition scheme. I08 keeps missing. ;TBT440,1 Correct error in initialization: 18 was not being put into denom. ;TBT439 Add 1 to Reg B cnt for DJNZ loop in Info const. Seems to run OK. ;TBT438 Try pgm w/o the jump around the OSW Instr Info byte interpretation. ; A little prob when SYNC not locked. A random count is used for the ; Reg A shift. ;TBT437 OSW Instr Byte Table needs to have SYNC Instr byte as first entry ; at the label. ;TBT436 Data is now being output on PIO B properly. ;TBT435 Finish up data reconstruction. Sync failed to lock first time out. ; Fixed problem, I failed to point to Reg C bit cnt - Branched around ; Info construction. ;TBT430,1,2,3,4 Derived from 426. Next up is incorporation of code to ; reconstruct OSW serial data word. ;TBT426 Dress up - get rid of dead code, comments. Ran OK ;TBT425 Put initialization back in - ran OK ;TBT423,424 Had a bad Z-80 CPU- became a problem as it warmed up. ;TBT422 Mon morning (4-20-92) it is working! ;TBT420 Derived from 408. ;TBT408 Looking better. ;TBT407 The clk correct in PIO routine seems a little shaky. ;TBT406 Re-arrange CTC routine- worked first time out!! ;TBT405 ;TBT404 Remove JP in CTC 0 int: occasional FALSE SYNC outputs, infrequent ; SYNC FOUND outputs. ;TBT403 Initial problem was found: ; extensive work on the 41X, 42X and 43X series revealed problem was ; with INTVTB not originating at 0100H. ;TBT402 Try the new technique using HL as a pointer instead of using ; explicit registers. ;TBT400,1 Begin implementing changes towards assembling data in memory. ;TBT305 Spruce up comments. ;TBT304 Comment out NOP prior to wait loop HALT. Looks good - occasional ; 'neg edge' triggering of PIO probably due to the 15 - 20 uS fall ; time - better comparator would probably help ;TBT302,3 Use 8:18 in CTC TC routine ;TBT302 Didn't change counts in PIO A INT routine, RAN OK after change. ; TBT301 Update ratiometric count scheme for 2.56 MHz clock ; Refer to file DTCTC8 for computations. Turns out the inst following ; the HALT inst is executed after returning from INT service!! ; New values in ratiometric scheme look good!! ; TBT300 Metrics: Measure amount of time we spend in loop waiting for CTC. ; TBT210 5-23-92 Freqs for cnt with 4 MHz clock yields: (approx 350 nS pulse) ; -------- projection for SCF ----------- ; Cnt Freq /50 /100 /2/50 /2/100 ; ------------------------------------------------------- ; 1 250 5 2.5 2.5 1.25 KHz ; 2 125 2.5 1.25 1.25 .625 ; 3 83.333 1.666 .833 .8333333 .41666 ; 4 62.5 1.25 ; LS Data ; -------- projection for SCF ----------- ; Presc Cnt Freq /50 /100 ; ------------------------------------------------------------- ; /256 1 15.625 312 156 Hz ; ; /16 25 10.000 200 100 ; /16 20 12.500 250 125 ; /16 18 13.888 277 138 ; /16 17 14.705 294 147 ; /16 15 16.666 333 166 ; /16 13 19.230 384 192 ; ; ; TBT206,7 4-11-92 Actuate all CTCs and create CTC test. Ran OK!! ; TBT205 Load other CTC's (CT0 doesn't want to work). Discovered that ; reset ckt (R and C) won't cut it - CPU and CTC do erratic ; things. ; TBT101,2 Incorp addrs Ctl wd defs From Tracker board test 102 ; TM0741 Copied from TM0732, Chg PIO B output to Mode 0 ; TM0732 Remove PIOB output in PIO INT routine. Ran OK!!! ; TM055, Corr. use of CTC reset ; TM054, Corr. error: not reloading 43 or 44 after loading 20 ; 11-25-90 ; TM053, 1st working copy made ; TM052, Incorporate search for edges (using PIO) ; ; ********* Include files ********** include ASCII.z ; Address definitions: RAMSTR EQU 01000H ;RAM Start addrs ; 4-Char ASCII Display address: ; Digit 3 is left-most digit, Digit 0 is rightmost digit ASCDSPCA EQU 2000H ; ASCii DiSPlay Control Address ASCDSPC0 EQU 2004H ; ASCii DiSPlay char 00 right-most ASCDSPC1 EQU 2005H ; ASCii DiSPlay char 01 ASCDSPC2 EQU 2006H ; ASCii DiSPlay char 02 ASCDSPC3 EQU 2007H ; ASCii DiSPlay char 03 left-most ; Address definitions: bit usage: x x x x x x Ctl/Dat B/A PIOAD EQU 00H ; PIO A Data PIOAC EQU 02H ; PIO A Ctl PIOBD EQU 01H ; B Data PIOBC EQU 03H ; B Ctl CT0 EQU 04H ; CTC 0 CT1 EQU 05H ; CTC 1 CT2 EQU 06H ; 2 CT3 EQU 07H ; 3 ; CTC Control Bytes, High Speed ;Timer Mode CTCEIHS EQU 81H ; En int, cont cnting, High Speed CTCDIHS EQU 01H ; Ds int, cont cnting CTCRS EQU 03H ; RESET, Ds int: requires CTCLDx to En again CTCLREHS EQU 87H ; Load, Reset, start cnting, En int CTCLRDHS EQU 07H ; Load, Reset, start cnting, Ds int CTCLCEHS EQU 85H ; Load, continue cnting, En int ;CTC Counter Mode Bit Definitions ; ; Pos/Neg Slope-||-Trigger--------------(Timer only) ; (Timer only)--Range-||||-Ld Time Constant----(Timer only) ; Counter/Timer Mode-||||||-Reset/NoReset ; Int En-||||||||-"1" ; 76543210 CTCCMEILP EQU 11010101B ; CTC Control Bytes, Low Speed CTCEILS EQU 0A1H ; En int, cont cnting CTCDILS EQU 21H ; Ds int, cont cnting CTCLRELS EQU 0A7H ; Load, Reset, start cnting, En int CTCLRDLS EQU 27H ; Load, Reset, start cnting, Ds int CTCLCELS EQU 0A5H ; Load, continue cnting, En int ; PIO Mode Control Bytes (MDCB) bit definition: m m x x 1 1 1 1 PIOMD0 EQU 00FH ; 0 output (can use ready/strobe handshaking) PIOMD1 EQU 04FH ; 1 input ditto PIOMD2 EQU 08FH ; 2 bi-directional using hndshk (port A only) PIOMD3 EQU 0CFH ; 3 individual pin I/O as set by IORCB which is sent ; following the MDCB, where input = 1, output = 0 ; PIO Int En/Dis byte bit definition: EnInt And/Or Hi/Lo Mask 0 1 1 1 PIODI EQU 003H ; PIODI byte PIOEI EQU 083H ; PIOEI follows ONE EQU 1 ZERO EQU 0 ; **** Begin PROM contents *** STARTPA: ORG 000H ;Hardware reset NOP ;1st instr to be executed DI ;2nd NOP NOP NOP JP PGMSTR ;jump over tables ORG 010H ;Address for 1st SYNC bit, val after decr ; ; OSW Instruction Byte Table bit usage/format: abcc cddd ; ; Where: hk = Sync period/Info/parity bit select ; bbb = bit position, 7-0 (left to right) in reconstructed RAM byte ; mmm = memory Byte sel for reconstruction, 0-4 (4.5 words req'd) ; --bit-- ; h k ; | SYNC 0 0 ; OSW Info 0 1 ; data Parity 1 0 ; | Spare 1 1 ; --- Count going into CT0HSI routine ; | Count coming out is 1 less than this ; | except for 1, where it is 84. ; | ; SYNC bits | Sync ; hkbbbmmm Cnt84 Sxx bit byte Value *Last* DEFB 00000111B ;01 S08 - - 0 *Next to last* DEFB 00000110B ;02 S07 - - 0 CLR OSWCST DEFB 00000101B ;03 6 - - 1 P OSW w/No Backgrd W ; DEFB 00000100B ;04 5 - - 1 P OSW ADDR ops DEFB 00000100B ;04 5 - - 1 N nothing ; DEFB 00000011B ;05 4 - - 0 P OSW DATA ops DEFB 00000011B ;05 4 - - 0 N ADDR ops DEFB 00000010B ;06 3 - - 1 N OSW w/No BackGnD W DEFB 00000001B ;07 S02 - - 0 Xor, Xfer DEFB 00000000B ;08 S01 - - 1 ; P = Proposed ; N = Now ;Odd parity bits ; hkbbbmmm Cnt84 Pxx bit byte DEFB 11101100B ;09 P37 5 4 Odd parity bits DEFB 11011100B ;10 P35 3 4 DEFB 11001100B ;11 33 1 4 DEFB 11111011B ;12 31 7 3 DEFB 11101011B ;13 29 5 3 DEFB 11011011B ;14 27 3 3 DEFB 11001011B ;15 25 1 3 DEFB 11111010B ;16 23 7 2 DEFB 11101010B ;17 21 5 2 DEFB 11011010B ;18 19 3 2 DEFB 11001010B ;19 17 1 2 DEFB 11111001B ;20 15 7 1 DEFB 11101001B ;21 13 5 1 DEFB 11011001B ;22 11 3 1 DEFB 11001001B ;23 9 1 1 DEFB 11111000B ;24 7 7 0 DEFB 11101000B ;25 5 5 0 DEFB 11011000B ;26 P03 3 0 DEFB 11001000B ;27 P01 1 0 Odd parity bits ; Bit weight: 421421 ; Odd Info bits ; hkbbbmmm Cnt84 Ixx bit byte DEFB 11101100B ;28 I37 5 4 FOB Flush out bit = 0 DEFB 11011100B ;29 I35 3 4 BP8 Blk par, Odd Info bits DEFB 11001100B ;30 33 1 4 BP6 DEFB 11111011B ;31 31 7 3 BP4 DEFB 11101011B ;32 29 - - BP2 DEFB 11011011B ;33 27 - - BP0 DEFB 01001011B ;34 25 1 3 C8 Freq/Dat, Odd info bits DEFB 01011011B ;35 23 3 3 C6 DEFB 01101011B ;36 21 5 3 C4 DEFB 01111011B ;37 19 7 3 C2 DEFB 01001010B ;38 17 1 2 C0 DEFB 01000001B ;39 15 0 1 A15 Addr, Odd Info bits DEFB 01010001B ;40 13 2 1 A13 DEFB 01100001B ;41 11 4 1 A11 DEFB 01110001B ;42 9 6 1 A09 DEFB 01000000B ;43 7 0 0 A07 DEFB 01010000B ;44 5 2 0 A05 DEFB 01100000B ;45 I03 4 0 A03 DEFB 01110000B ;46 I01 6 0 A01 ; Bit weight: 421421 ;Even parity bits ; hkbbbmmm Cnt84 Pxx bit byte DEFB 11100100B ;47 P36 4 4 Parity, Even Info bits DEFB 11010100B ;48 P34 2 4 DEFB 11000100B ;49 32 0 4 DEFB 11110011B ;50 30 6 3 DEFB 11100011B ;51 28 4 3 DEFB 11010011B ;52 26 2 3 DEFB 11000011B ;53 24 0 3 DEFB 11110010B ;54 22 6 2 DEFB 11100010B ;55 20 4 2 DEFB 11010010B ;56 18 2 2 DEFB 11000010B ;57 16 0 2 DEFB 11110001B ;58 14 6 1 DEFB 11100001B ;59 12 4 1 DEFB 11010001B ;60 10 2 1 DEFB 11000001B ;61 08 0 1 DEFB 11110000B ;62 06 6 0 DEFB 11100000B ;63 04 4 0 DEFB 11010000B ;64 P02 2 0 DEFB 11000000B ;65 P00 0 0 ; Bit weight: 421421 ;Even bits ; hkbbbmmm Cnt84 Ixx bit byte DEFB 11100100B ;66 I36 4 4 BP9 Blk Par, Even Info bits DEFB 11010100B ;67 I36 2 4 BP7 Block DEFB 11000100B ;68 32 0 4 BP5 Parity DEFB 11110011B ;69 30 - - BP3 Bits DEFB 11100011B ;70 28 - - BP1 DEFB 01000011B ;71 26 0 3 C9 | DEFB 01010011B ;72 24 2 3 C7 Freq DEFB 01100011B ;73 22 4 3 C5 Code or DEFB 01110011B ;74 20 6 3 C3 Status DEFB 01000010B ;75 18 0 2 C1 | DEFB 01100010B ;76 16 4 2 TYPE DEFB 01001001B ;77 14 1 1 A14 | DEFB 01011001B ;78 12 3 1 A12 | DEFB 01101001B ;79 10 5 1 A10 | DEFB 01111001B ;80 08 7 1 A08 Address DEFB 01001000B ;81 06 1 0 A06 | DEFB 01011000B ;82 I04 3 0 A04 | DEFB 01101000B ;83 I02 5 0 A02 | DEFB 01111000B ;84 I00 7 0 A00 | *Start* OSWIBT: DEFB 00000000B ;01 S08 - - 8th Sync bit (= 0) ; hkbbbmmm ; Bit weight:--421421 ; ORG 0100H - 10 ; ORG 080H ORG 066H ASCII 'TBT800' ; Pgm ID ; ORG 090H ORG 06CH ASCII ' (c) 1993 ' ;Copyright notice ASCII 'COPYRIGHT ' ;Copyright notice ASCII '1993 ' ASCII 'J.V.Poll' ; ORG 0100H ; ORG 008EH ; ; Setup Channel Freq list, xferred to RAM on power-up ; Allen/McKinney list: STCHFRQLS: DEFB 0CEH ;SYNBASEL - low byte DEFB 082H ;SYNBASEH - high byte DEFB 0 ;Shift DEFB 0 ;Spare DEFB 0EAH ;Ch 1 - low byte DEFB 002H ; .. - high byte DEFB 0 ;Shift DEFB 0 ;Spare DEFB 0FEH ;Ch 2 DEFB 002H DEFB 0 ;Shift DEFB 0 ;Spare DEFB 012H ;Ch 3 DEFB 003H DEFB 0 ;Shift DEFB 0 ;Spare DEFB 02BH ;Ch 4 DEFB 003H DEFB 0 ;Shift DEFB 0 ;Spare DEFB 02BH ;Ch 5 DEFB 003H DEFB 0 ;Shift DEFB 0 ;Spare ; ; Be sure to change the number of Bytes to be copied into RAM in code further ; down. ; The data in these lists are actually examined from RAM ; **Search starts here** CGLISTRRH: ;Call Group LIST Rom RH (LSH) DEFB 070H ;PFD DEFB 0D0H ;PPD Dispatch DEFB 0F0H ;CH A DEFB 010H ;CH B DEFB 0B0H ;Animal DEFB 030H ;NCIC DEFB 0F0H ;Spec DEFB 000H ; DEFB 000H ; DEFB 000H ; DEFB 000H ; DEFB 000H ; DEFB 000H ; DEFB 000H ; DEFB 000H ; DEFB 000H ; ORG CGLISTRRH+010H ;Call Group LIST Rom RH (LSH) CGLISTRLH: ;Call Group LIST Rom LH (MSH) DEFB 000H ; DEFB 000H ; DEFB 000H ; DEFB 000H ; DEFB 000H ; DEFB 000H ; DEFB 000H ; DEFB 000H ; DEFB 000H ; DEFB 003H ;Spec DEFB 003H ;NCIC DEFB 008H ;Animal DEFB 002H ;PCH B DEFB 001H ;PCH A DEFB 001H ;PPD Dispatch TBT784 DEFB 001H ;PFD ;**Note: Search starts here** ; ORG 0140H ; ORG 00B0H ORG CGLISTRLH+010H ;Calc new offset addr CGLISTRCHL: ;Call Group LIST Rom CHanneL ; ;Begins this end ASCII 'P FD' ASCII 'P PD' ASCII 'Ch A' ASCII 'Ch B' ASCII 'AniC' ASCII 'NCIC' ASCII 'Spec' ASCII ' ' ASCII ' ' ASCII ' ' ASCII ' ' ASCII ' ' ASCII ' ' ASCII ' ' ASCII ' ' ASCII ' ' ; If required for diagnostic purposes ... ; This table has been moved to RAM - contents are copied to RAM from PROM ;INTVTB: ; ***** INT Vector TaBle ***** Int service addrs ;SIOB INT service ; DEFW 0 ; SIO B XMT buffer empty ; DEFW 0 ; SIO B external status change ; DEFW 0 ; SIO B RCV data avail ; DEFW 0 ; SIO B special RCV condition ; ORG 0108H ;SIOA INT servive ; DEFW 0FF08H ; SIO A XMT buffer empty ; DEFW 0FF0AH ; SIO A external status change ; DEFW 0FF0CH ; SIO A RCV data avail ; DEFW 0FF0EH ; SIO A special RCV condition ORG 0110H ;Synthesizer Reference frequency REFFREQ0: DEFB 009H ;Most sig byte ** Accessed by EPROM routines* REFFREQ1: DEFB 0C0H ;Least sig byte ;Calc'd Synthesizer frequency is in RAM ... ZYNFREQ0: DEFB 084H ;Most significant byte ** Diagnostic aid ** ZYNFREQ1: DEFB 095H ;Least significant byte ** Diagnostic aid ** ; Define freq constants ; FREQuency Offset Low/High ** Diagnostic aid ** ;FREQOFFL: DEFB 04EH ;Ch 4 - '14E' hex, low byte ;FREQOFFH: DEFB 001H ; .. high byte ; McKinney: ;SYNBASEL EQU 047H ;Syn base freq - Low byte ;SYNBASEH EQU 083H ; .. high byte ; Plano: ;SYNBASEL EQU 0CEH ;Syn base freq - Low byte ;SYNBASEH EQU 082H ; .. high byte ; ORG 00C4H ; ORG 00D0H ; ; Codes based on frequency observed for PLANO ; This table is searched for matching codes. When a matching code is found, ; the channel number is returned and used to point to the frequency table ; for programming the Scanner's synthesizer. FRQLISTRRH: ;FReQ LIST Rom RH DEFB 0D6H ; 1 **Search starts here** DEFB 0D7H ; 2 DEFB 0EAH ; 3 DEFB 0EBH ; 4 DEFB 035H ; 5 DEFB 000H ; 6 DEFB 0CAH ; 7 DEFB 000H ; 8 DEFB 0E3H ; 9 DEFB 0E4H ; 10 FRQLISTRLH: ;FReQ LIST Rom LH DEFB 003H ; 10 DEFB 003H ; 9 DEFB 000H ; 8 DEFB 003H ; 7 DEFB 000H ; 6 DEFB 003H ; 5 DEFB 002H ; 4 DEFB 002H ; 3 DEFB 002H ; 2 DEFB 002H ; 1 **Search starts here** FRQLISTRCOR: ;FReQ LIST Rom CORrected DEFB 0D6H ; 1 Low Byte DEFB 002H ; High Byte DEFB 0D7H ; 2 DEFB 002H ; DEFB 0EAH ; 3 DEFB 002H ; DEFB 0EBH ; 4 DEFB 002H ; DEFB 0FEH ; 5 DEFB 002H ; DEFB 0FFH ; 6 Low Byte DEFB 002H ; High Byte DEFB 012H ; 7 DEFB 003H ; DEFB 013H ; 8 DEFB 003H ; DEFB 02BH ; 9 DEFB 003H ; DEFB 02CH ; 10 DEFB 003H ; ;*** Program origin ******************* ORG 0140H ; Org had been 0120H TBT790 ; ORG 0160H ; Org had been 0200H TBT783 ; ORG 0120H ; Org had been 0200H TBT785 PGMSTR: DI ;Disable interupts and IM 2 ;..set Z80 for Mode 2 Interupts LD SP,RAMSTR+07FFH ;Load stack pointer with last RAM addr ;*** Begin: Int Vector Table Setup *** LD HL,INTVTB ;Get 16-bit INTerrupt Vector TaBle addr LD A,H ;..get the high byte LD I,A ;..put it into the "I" (interupt) reg ;*** End: ***************************** ;*** Begin: CTC setup ******************** ; CTC Int Vector setup LD A,30H ;Load lower 8 bits of int vector and OUT (CT0),A ;..output as base addr for the CTCs ; Reset all Counter Timer Chips Assignments: LD A,CTCRS ;Reset CTC 0 Main HS/LS timing/sampling OUT (CT0),A LD A,CTCRS ;Reset CTC 1 Disconnect timing/sampling OUT (CT1),A LD A,CTCRS ;Reset CTC 2 SCF clock OUT (CT2),A LD A,CTCRS ;Reset CTC 3 Syn enable line monitor OUT (CT3),A ;*** End: CTC setup ********************* ;*** Begin: PIO A setup ****************** ; ; Propsed: 11-02-92 ; ; Bit defs: ; Squelch|--Keyboard---|---- From Scanner/Rcvr ----|From SCF & | ; In |---SW IN ----| Processor |Comparator | ; 2 | 1 0 | | ------ ; 7 | 6 5 | 4 3 2 1 | 0 | ; SQ_IN SWIN1 SWIN0 Shift Enable Data Clock Trunk ; ; Switches: ; |---Select---| ; ; | ^ ; Was: SWIN2 \ | ; ; SWIN1 -- <-- --> ; ; SWIN0 -- Mode Enter ; ; | | ; | | ; PioB-5 -- --PioB-6 ; ; LD A,PIOMD3 ; MDCB: MODE 3 - IORCB must follow ... OUT (PIOAC),A LD A,11111111B ; IORCB In=1, Out=0 - follows MDCB3 TBT701 OUT (PIOAC),A LD A,038H ; INTVB - Inter Vector Byte, LS 8 bits OUT (PIOAC),A ; Believe following can be called when needed to define which bits ; are to be active for interrupts. ; LD A,0B7H ; INTCB - Mask Byte must follow ... ; OUT (PIOAC),A ; LD A,0FEH ; MASKCB, must follow INTCB (TBT700: 0FEh) ; OUT (PIOAC),A ;Place address of ISR into RAM ; LD HL,PIOAxxxx ;PIO A Interrupt Service Address ; LD (PIOAIV),HL ;Out to PIO A COntrol address ; For test purposes: ; LD A,PIODI ; Diasable PIO int ; OUT (PIOAC),A ;*** End: PIO A setup ******************* ;*** Begin: PIO B setup ***************** ; ; Proposed: 10-19-92 ; ; Bit defs: ; |--Keyboard---|-------- To Scanner/Rcvr --------| ; | -SW OUT- | |---- To LO Synthesizer ----| ; | 1 0 | | | ; 7 | 6 5 | 4 | 3 2 1 0 | ; Spare SWO1 SWO0 Mute Shift Enable Data Clock ; LD A,PIOMD3 ; MDCB: MODE 3 - IORCB must follow ... OUT (PIOBC),A LD A,10000000B ; IORCB In=1 Out=0 - follows MDCB3 TBT701 OUT (PIOBC),A LD A,PIODI ; INT Disable OUT (PIOBC),A ;*** End: PIO B setup ********************************* ; *** Begin: Initial PIO B output set up ************** ; Bit defs: x x x MUTE SHFT EN DAT CLK ; Preset bits: x x x 1 0 0 0 1 XOR A ;Clr reg A ; OR 00010001B ;Set Mute and Clk bit high OR 00110001B ;Set Mute and Clk bit high TBT739 LD (OLDSDATA),A ;Save in old serial data TBT733 OUT (PIOBD),A ;Output data JR TITLEMAIN ; *** End: Initial PIO B output set up **************** ;*** Begin: ************************* ; POLLTL: ASCII 'POLL' LABSTL: ASCII 'LABS' TITLEMAIN: ; LD A,083H ; Clear display, set for max brightness ; LD (ASCDSPCA),A ; Output to display's Control Address ;Four-Character ASCII Display Setup -Req'd- ; Control --Blink (if = 1) C-Cursor: 0xx=disable ; \\ | 101=Blink single char ; \\|CCCBB B - Brightness 111=char/cursor alternate ; 76543210 100=cursor only (all on) LD A,00011111B ; Blink single char, set for max brightness LD (ASCDSPCA),A ; Output to display's Control Address LD HL,POLLTL ;Get title address CALL DATATODISP ;Output display data ;Delay LD IX,0FC00H ;Init for outer loop LD DE,1 POLLTD: LD B,255 ;Inner loop DJNZ $ ADD IX,DE JP NC,POLLTD LD HL,LABSTL ;Get title address CALL DATATODISP ;Output display data ;*** End: ********************* ;*** Begin: ************************* ; Copy ROM frequency data into RAM ; LD HL,STCHFRQLS ;Get SeTup CHan FReQ LiSt beginning addr in ROM LD DE,STCHFRQLRA ; ... List RAm addr ; LD BC,20 ;5CH * 4_bytes for Allen/McKinney system LD BC,24 ;6CH * 4_bytes LDIR ;Move f/ROM to RAM LD A,5 LD (STCHFPMX),A ;Get SeTup CHannel Freq Pointer ToP max val ;*** End: ********************* ;*** Begin: ************************* ; Copy ROM CG LIST into RAM ; LD HL,CGLISTRRH ;Get list starting address in ROM LD DE,CGLISTRH ;Get list destination address in RAM ; LD BC,5 ;#bytes ; LD BC,32 ;#bytes LD BC,32+4*16 ;#bytes LDIR ;Move f/ROM to RAM ; LD HL,CGLISTRLH ;Get list starting address in ROM ; LD DE,CGLISTLH ;Get list destination address in RAM ; LD BC,5 ;#bytes ; LDIR ;Move f/ROM to RAM ;*** End: ********************* ;*** Begin: ************************* ; Clear RAM ; DATAEBCLR: ;DATA Enter Buffer CLeaR routine LD HL,DATAEBUF ;Get buffer addrs in RAM XOR A ;CLR A LD B,4 ; 4-3 3-2 2-1 0-1 DATAEBCLR1: ;Loop destination LD (HL),A INC HL DJNZ DATAEBCLR1 ;*** End: ********************* JP MODE1CD ;To MODE SEL first **TBT756 ;*** Begin: TRacK INITialization *********************** ; Init variables in preparation for Tracking loop TRKINITL: ;TRAK MoDe TitLe ASCII 'OK ' TRKINIT: LD HL,TRKINITL ;Get title address CALL DATATODISP ;Output display data ;TRKINIT: LD HL,CT0HSIVA ;CTC 0 Int variables LD (HL),40 ;Cnt84 (circular) INC HL LD (HL),18 ;Denominator count (circular) ;Set up initial conditions for HS data sampling CALL PIOASUTRK ; PIO A Set Up TRaK, INTCB MASKCB set up CALL HSIRSU ; Do: HS Int Routine SetUp ;* CALL LSIRSU ; Do: LS Int Routine SetUp ** Diagnostic XOR A ; CLR Reg A New TBT701 ; LD (TRAKMD1),A ; Clr CHange MODE flag LD (C0HSSWDT),A ; Clr Ctc 0 HS SWitch DaTa flag LD (MDSWDAT0),A ; Clr MoDe SWitch DATa 0 LD (MDSWDAT1),A ; Clr MoDe SWitch DATa 1 INC A ; TBT764 LD (STCHFPTR),A ; Init SeTup CHannel Freq PoinTeR CALL STCHPTBC ; Program frequency into scanner ;*** End: TRacK INITialization ************************* LD A,1 LD (INCCNT),A ;*** Begin: Tracking Main program **************************** ; ; Main program loop executed AFTER an interrupt is executed. The possible ; interrupt routines include HS CTC 0 service, PIO A service and LS CTC0 and ; CTC1 service. ; ; Program operation. ; 1) Set up CTC and PIO for HS operation and program Rcvr Synthesizer ; w/frequency data. ; 2) Wait at bottom of Main program loop for an interrupt to occur ; 3) Upon occurance of an interrupt, service the HS CTC 0 or HS PIO ; routines. These routines set flags which are then inspected in ; the Main program below. ; 4) If HS SYN ABsent flag is set secure next possible Setup Channel from ; list and repeat 1) through 5). ; 5) While in HS Select perform HS OSW acquisition, HS OSW screening and ; Call Group matching. When a Call Group match is found set up CTC and ; PIO for LS operation and program Rcvr Synthesizer w/frequency data and ; perform setps 5) through 6). ; 6) LS SYNc Qualifying much as HS SYNC Qual ; When too many LS Sync Sequences missed return to Setup CH (set GOTOSC ; flg step ; 7) If DiSconnect SEQuence is received return to Setup CH (set GOTOSC flag) ; ; Synopsis: Setup-Channel Search ; Select first channel in group ; Qualify HS Sync (in CTC 0 Int service routine) ; Observe HSSYNAB flag ; No HS Sync- move on to next channel ; HS Sync found- perform programmed actions (look for programmed OSW addrs) ; TRKWAITLP: ; Tracking WAIT LooP NOP DI ;No interrupts during following ;**Begin: Read mode switch *************** LD A,(C0HSSWDT) ; Load Ctc 0 HS SWitch DaTa CP 1 ; Compare JP Z,MODE1CD ; ** Diagnostic aid ** ;**End: Read mode switch ***************** ; DI ; TBT734 LD A,(HSSYNAB) ;Get High Speed SYNc ABsent flag CP 1 ;If flag set, point to next SC ... CALL Z,INCRSCPTR ;.. by INCRementing Setup Channel PoinTeR, ;.. resetting HSSYNAB and setting GOTOSC LD A,(GOTOSC) ;Flag to go to Setup Channel CP 1 ;Set? CALL Z,GOTOSCFPTR ;Yes, GOTO Setup Channel Freq PoinTeR ;In lieu of below: GOTOSC flag in is set in CT0LSxx routine. ; LD A,(LSSYNAB) ;Get Low Speed SYNc ABsent flag ; CP 1 ;If flag set, ... ; CALL Z,GOTOSCFPTR ;GOTO Freq List Offset PoinTeR LD A,(GOTOVC) ;Flag set in HS data compare routine CP 1 JP NZ,TKWAITLP01 ;If flag not set, skip ahead. ;**Begin: Prepare for Voice Channel CALL LSIRSU ; Set up LS Int Routine LD A,(SYNFSHFTRA) ; Get /SYN Freq SHiFT bit (5/12.5 KHz down) ; XOR 001H ; Invert LSB TBT766 LD (OSWXOUT+4),A ; Save ; ; LD BC,OSWXOUT+2 ; Pointer to Voice Channel data LD BC,OSWXOUT+2 ; Pointer to Voice Channel data CALL CALCOUTSYN ; Output data to Syn in radio LD A,(OLDSDATA) ;Get old serial data AND 00001111B ;Set MUTE false (low) LD (OLDSDATA),A ;Save OUT (PIOBD),A ;**End: Prepare for Voice Channel TKWAITLP01: ; WAIT LooP 01 ;**Begin: Diagnostic aid ** LD A,(INCCNT) ;Incrementing count for RLCA TKWAITLP02: ; WAIT LooP 02 LD (INCCNT),A ;**End: Diagnostic aid ** TKWAITLP03: ; WAIT LooP 03 EI ; Enable interrupts now HALT ; Program halts here pending interrupt occurance JP TRKWAITLP ;This instr executed after ret from INT serv ;*** End: Tracking Main program ****************************** ;*** Begin: MODE Select Code *********************************** ; ; Proposed interrupt structure: ; PIO A - CLK line Monitor (also trunk data HS LS timing) ; CTC 3 - ENable line monitor (also Disconnect Sequence timing) ; CTC 1 - Keyboard interrupt timer, cycles through every so often ; to read Keyboard switchs. ; MODETBL1: ;MODE TaBLe ASCII 'TRAK' ;Track mode DEFW TRKINIT ;Track routine address ASCII 'CGrp' ;Call Group DEFW CALLGRP ;CALL GRouP routine ASCII 'StCh' ;Read Synthesizer for SeTup CHannel list DEFW RSDWL ; ASCII 'SCAN' ;SETuP or configure ; DEFW SCANINIT ;Mode select Address ; DEFW STARTPA ;Program START Addrs ; ASCII 'VIEW' ;SETuP or configure ; DEFW VIEWINIT ;Mode select Address ; DEFW STARTPA ;Program START Addrs ; Diagnostic modes: ; ASCII 'RSYN' ;Read Synthesizer ; DEFW RSDWL ; ASCII 'DATA' ; ; DEFW DATAENT ;DATA ENTer routine ASCII 'RST ' ;Reset DEFW STARTPA ;Program START Addrs DEFB 0FFH ;End identifier MODE1CD: CALL KYBTISU ;Start Keyboard int CTC 1 SW data: 0000 LMRE XOR A LD (C0HSSWDT),A ;Clr Ctc 0 HS SWitch DaTa (Set in Track code) LD (MDSWDAT1),A ;Clr data MODE1CD1: ;Loop dest 'till mode key clears. EI LD A,(MDSWDAT1) ;Hold loop, until mode key clears CP 0 ;Looking to branch as long as data is NULL JP Z,MODE1CD1 ;..waiting for it to change when key is ;..released. ;Present state: MDSWDAT1 changed from Null DI XOR A ;Clr Reg A LD (MDSWDAT1),A ;Clr data again before proceeding below.. ;******************* MODE1CD2: ;Loop destination XOR A ;Init LD (MODEPTR),A ;.. Mode PoinTeR LD (MODEPTRX6),A ;.. and X 6 Mode PoinTeR LD HL,MODETBL1 ;Output MODE CoDe Table 1st data item CALL DATATODISP MODE1CD3: ;Loop destination CALL RDMDSWDAT ;Data ret in Reg A: SW data: 0000 LMRE ; CP 00000100B ;Look for Mode Key ; JP Z,TRAKMDL ;To ... ; LMRE CP 00001000B ;Look for Left key CALL Z,MODEPINC ;To MODE pointer increment CP 00000010B ;Look for Right key CALL Z,MODEPINC ;To MODE pointer increment CP 00000001B ;Look for Enter key JR Z,MODEEXE ;To MODE EXEcute EI ;Enable interrupts HALT ;Wait here for CT1 Keyboard routine interrupt. JP MODE1CD3 ;This instr executed after ret from CT1KTI ;****** ;*** Begin: MODE EXEcute *** MODEEXE: LD HL,MODETBL1 ;Get starting address of MODE TaBLe LD A,(MODEPTRX6) ;Get X 6 mode pointer ADD 4 ;Point to the associated addrs CALL ADDATOHL LD E,(HL) INC HL LD D,(HL) EX DE,HL ;Swap DE and HL, 4-T states! JP (HL) ;Execute ;*** End: MODE EXEcute *** ;*** Begin: MODE Pointer INCrement *** MODEPINC: LD A,(MODEPTR) ;Get mode pointer INC A ;Update LD B,A ;Save for later SLA A SLA A ; X 4 ADD B ; X 5 ADD B ;Total multiply is six LD (MODEPTRX6),A ;..save it LD (DIAG05),A ; ** Diagnostic aid ** ;Replace this with a fetch from RAM: LD HL,MODETBL1 ;Get starting address of MODE TaBLe CALL ADDATOHL ;A+HL--> HL LD A,(HL) ;Get next data item pointed to by HL LD (MODETTL),HL ;.. and also save CP 0FFH ;Is it the end identifier? JR NZ,MODEPINC1 ;JR ahead LD HL,MODETBL1 ;Get starting address of MODE TaBLe XOR A LD (MODEPTRX6),A ;Clr 5X pointer LD B,A MODEPINC1: LD A,B LD (MODEPTR),A ;Put back CALL DATATODISP ;Addrs in HL points to string RET ;*** End: MODE Pointer INCrement *** ;*** End: MODE 1 CoDe ************************************* ;*** Begin: RST MoDe *********************** ; ; ;RSTMODE: ; LD HL,RSTMDTL ;Get address of title ; CALL DATATODISP ; ;RSTMODE1: ;Loop dest ; CALL RDMDSWDAT ;Data ret in A: SW data: 0000 LMRE ; ; CP 00000001B ;Enter Key ; JP Z,STARTPA ; To program start ; ; CP 00000100B ;Mode Key ; JP Z,RSDWL ;Advance to Read Syn Data select ; ; EI ; HALT ; JP RSTMODE1 ;*** End: RST MoDe ********************************* ;*** Begin: Read Syn Data Wait Loop *********************** ; ** This is not actually a 'wait loop'. ; ; Interrupts occur in this loop to: ; ; 1) Respond to CLK line going true to read the serial data output by the ; processor (normally to Rcvr's LO Synthesizer). ; 2) Respond to ENable line going true (signaling that all bits for /R or ; /N divisor are in). ; RSDWL: CALL RSDISU ;Do: Read Serial Data Int Set Up RSDWL1: ;Loop dest CALL RDMDSWDAT ;Data ret in A: SW data: 0000 LMRE ; LMRE CP 00000100B ;Mode Key JP Z,MODE1CD2 ;Return to MODE select ; JP Z,DATAENT ;Advance to DATA ENTer select ; CP ENTER_KEY ; = 0000 0001B CP 00000001B ;Enter Key JP Z,RDSFRQ ;to ... EI HALT ;Wait for int to occur JP RSDWL1 ;Inst executed after ret from int ;*** End: Read Syn Data Wait Loop ************************* ;*** Begin: CALL GRouP routine **************************** CALLGRP: ;Edit/review Call Group names and codes LD A,15 ;This will roll over from 15 back to zero LD (CGRPCHPTR),A ;..when INCCGRPP is called XOR A LD (CGDATAPIFLG),A ;Clr flag that indicates Return key LD A,020H ;Clear buffer LD (BUF3BLNK+0),A ;Place into last char posn LD (BUF3BLNK+1),A ;Place into last char posn LD (BUF3BLNK+2),A ;Place into last char posn ;Initial display CALL INCCGRPP ;INCr Call GRouP Pointer ; XOR A ;Clr flag indicating next ENT key is to ; LD (CGDATAPIFLG),A ;..activate code operating on CG Name CALLGRP1: ;Loop dest CALL RDMDSWDAT ;Data returned in A: (SW data) = 0000 LMRE CP 00000100B ;Mode Key JP Z,MODE1CD2 ;Back to MODE select CP 00000001B ;Enter Key, to next data item CALL Z,INCCGRPP ;INCr Call GRouP Pointer CP 00000010B ;Right Key, to next data item CALL Z,INCCGRPCHRP ;INCr Call GRouP CHaR Pointer CP 00001000B ;Up/Lt Key, incr data item CALL Z,INCCGCHR ;INCr Call GRouP CHaRacter EI HALT ;Wait for int to occur JP CALLGRP1 ;Inst executed after ret from int ;***End ;***Begin: INCr Call GRouP Name/Code Pointer ********* ; INCCGRPP: LD A,(CGDATAPIFLG) ;Examine flag that indicates Return key CP 1 ;was depressed JP Z,CGRPCODE ;Go operate on Hex Call Group data. XOR A ;Initialize pointer to point to 1st char LD (INCCGRPCHRPC),A ;.. within the 4-char area of operation. LD A,(CGRPCHPTR) ;Get pointer offset into CHannel assignment INC A CP 16 ;Maximum number of Call Groups JR NZ,INCCGRPP1 ;INCr Call GRouP Pointer XOR A ;Clr A INCCGRPP1: ;JP dest LD (CGRPCHPTR),A ;Save pointer offset ;Now convert pointer to an ASCII character CALL CNVINTASC ;I/O: Reg A, IN=0-F, OUT=ASCII equivalent LD (BUF3BLNK+3),A ;Place into last char posn LD HL,BUF3BLNK ;Get addrs CALL DATATODISP ; CALL DELAY ;Display it for a couple of secs ;Now display Channel Name LD A,(CGRPCHPTR) ;Get pointer offset into CHannel assignment SLA A ;Multiply by 2 SLA A ;.. tot of 4 LD HL,CGLISTCHL ;Get addrs of Call Group LIST CHanneL in RAM CALL ADDATOHL ;Add Reg A and HL, result in HL CALL DATATODISP ;Output the name LD A,0 ;Force 1st digit to blink CALL BLINK ;Reg A indicates char to blink: 0-L 1 2 3-R LD A,1 ;Set flag indicating next ENT key is to LD (CGDATAPIFLG),A ;..activate code operating on HEX Call Group RET ;***End: ********* ;***Begin: ********* CGRPCODE: ;Display/edit Call group codes ;Get Call Group Code from List ; Break up each of the two bytes into two nibbles ;Display the Hex CG code by calling DATAEBDSP which outputs the ; nibbles to the display. ; ;Get high byte and convert to two nibbles LD HL,CGLISTLH+15 ;Call Group LIST Left (MS) Half ;Search DECrements from this location LD A,(CGRPCHPTR) ;Get pointer offset into CHannel assignment CALL SUBAFRHL LD A,(HL) ;Get MSH (Left) half AND 11110000B ;Keep only Left four bits RLCA ;Move over to the right position RLCA RLCA RLCA LD (DATAEBUF),A ;Place nibble into buffer LD A,(HL) ;Get MSH (Left) half AND 00001111B ;..keep only right four bits LD (DATAEBUF+1),A ;..place in buffer ;Get Low byte and convert to two nibbles LD HL,CGLISTRH ;Call Group LIST Right (LS) Half ;Search INCrements from this location LD A,(CGRPCHPTR) ;Get pointer offset into CHannel assignment CALL ADDATOHL LD A,(HL) ;Get Right half AND 11110000B ;Keep Left half of LSByte RLCA RLCA RLCA RLCA LD (DATAEBUF+2),A LD A,(HL) ;Get Right half AND 00001111B ;Keep Right half of LSByte LD (DATAEBUF+3),A ; LD HL,DATAEBUF ; CALL DATATODISP ; CALL DATAEBDSP ;DATA Enter Buffer to DiSPlay XOR A ;Clr flag indicating next ENT key is to LD (CGDATAPIFLG),A ;..activate code operating on CG Name LD (INCCGRPCHRPC),A ;Clr cnt within the 4-char area of operation. ; XOR A ;Force 1st digit to blink *If inst. req'd* CALL BLINK ;Reg A indicates char to blink: 0-L 1 2 3-R RET ;***End: *********************** ;***Begin: INCr Call GRouP CHaR Pointer ********* ; Action: Incr a 0-3 count used as an index along with base addr into ; the 4-byte name area in RAM and move the blinking cursor circularly. INCCGRPCHRP: LD A,(INCCGRPCHRPC) ;Get count LD B,A ;Save old count CALL UNBLINK LD A,B ;Get saved old count INC A CP 4 JR NZ,INCCGRPCHRP1 XOR A INCCGRPCHRP1: LD (INCCGRPCHRPC),A ;Save count CALL BLINK ; LD A,(CGRPCHPTR) ;Get pointer offset into CHannel assignment ; LD HL,CGLISTCHL ;Get addrs of Call Group LIST Rom CHanneL RET ;***End ;***Begin: INCr Call GRouP CHaR ********* ; Implementation: Get data from position in RAM, incr according to algorithym, ; then replace in RAM INCCGCHR: LD A,(CGDATAPIFLG) CP 1 JP NZ,CGRPCODEIC LD A,(CGRPCHPTR) ;Get pointer offset into Call Groups SLA A ;Multiply by 2 SLA A ;.. tot of 4 LD HL,CGLISTCHL ;Get addrs of Call Group LIST CHanneL CALL ADDATOHL ;Add Reg A and HL, result in HL PUSH HL ;Save this computed base address POP DE ;.. in DE pair ;Reg HL now contains pointer to beginning ;..of four character block. Next ;..calculate pointer to individual character LD A,(INCCGRPCHRPC) ;Get count CALL ADDATOHL ;A+HL->HL LD A,(HL) ;Get char (Space, !, ", # ... x, y, z) INC A ;Incr CP 07FH ;Won't allow over ... JR NZ,INCCGCHR1 ;JR ahead if ... LD A,020H ;Load A INCCGCHR1: LD (HL),A ;Put Char back EX DE,HL ;Get character-block starting addrs CALL DATATODISP ;Display data RET ;***** CGRPCODEIC: ;Call GRouP CODE Inc hex Char CALL DATAENIC ;Incr number in DATAEBUF at ptr and DISP it LD A,(INCCGRPCHRPC) ;Get position: decide which byte to work on CP 2 ;CY bit set when A < Operand JR NC,CGRPCODEIC1 ;Jump ahead if NO CY meaning: A > Op ;Present state: CY set (Reg A) = 0 or 1 ;Digits L-R --> 0 1 2 3 LD HL,CGLISTLH+15 ;Get Call Group LIST Left (MS) Half addrs ; For LH search starts from top, sub offset LD A,(CGRPCHPTR) ;Get pointer offset into Call Groups CALL SUBAFRHL ;Calc addrs in HL pair EX DE,HL ;..and save in DE pair LD HL,DATAEBUF ;Src Addrs for High (MS) Code nibble ; needed in HL for Logical OR JR CGRPCODEIC2 ;Join operations below ;Present state: CY not set (Reg A) = 2 or 3 CGRPCODEIC1: ;Call GRouP CODE Inc hex Char LD HL,CGLISTRH ;Call Group LIST Right (LS) Half ; For RH, search INCrements from bottom LD A,(CGRPCHPTR) ;Get pointer offset into CHannel assignment CALL ADDATOHL ;Addrs in HL EX DE,HL ;Save in DE LD HL,DATAEBUF+2 ;Src Addrs for Low (LS) Code nibble ; needed in HL for Logical OR CGRPCODEIC2: ;Present state: ; Src HL ; Dest. Addrs in DE, ;Pull together bytes from DATAEBUF into A for storage at DE LD A,(HL) SLA A ;Move nibble into MSB position SLA A SLA A SLA A INC HL ;Point to next buffer OR A,(HL) ;Combine high nib (in A) w/ low nib LD (DE),A ;Put byte into calc'd addrs RET ;***End: INCr Call GRouP CHaR ********* ;*** End: INCr CG Pointer ************************* ;*** Begin: DATA ENTer routine **************************** ; ; Enter 4 Hex chars into a buffer. ; This is done by using the 4 buttons to: ; Shift the char being worked on ; Incr the char from 0 thru 9 to A thru F back thru 0 etc ; ; DATAENT: ;Advance to DATA ENTer select ; Control --Blink (if = 1) C-Cursor: 0xx=disable ; \\ | 101=Blink single char ; \\|CCCBB B - Brightness 111=char/cursor alternate ; 76543210 100=cursor only (all on) ; LD A,00011111B ; Blink single char, set for max brightness ; LD (ASCDSPCA),A ; Output to display's Control Address ; ; XOR A ;Init pointer to char in buffer ; LD (DATAEBUFP),A ;pointer ; ; CALL DATAEBDSP ;Display data TBT778 ; LD A,(DATAEBUFP) ;Get char pointer ; CALL BLINK ;Set bit in D7 in DATAEBUF at DATAEBUFP ; DATAENT1: ;Loop dest ; CALL RDMDSWDAT ;Data returned in A: (SW data) = 0000 LMRE ; ; CP 00000100B ;Mode Key ; JP Z,MODE1CD2 ;Back to MODE select ; ;; CP 00000001B ;Enter Key, to next data item ;; JP Z,DATAEN ;to ... ; ; CP 00000010B ;Right Key ; CALL Z,DATAENICP ;Incr character position ; ; CP 00001000B ;Left (up) Key ; CALL Z,DATAENIC ;Incr character ; ; EI ; HALT ;Wait here for int ; JP DATAENT1 ;Ret f/interrupt executes this instruction. ;*** End: DATA ENTer ************ ;*** Begin: DATA ENtry Incr Character Position *** ; DATAENICP: ;Incr character position ; LD A,(DATAEBUFP) ;Get char position in buffer ; INC A ;Incr ; CP 4 ;Won't allow over 3 ; JR NZ,DATAENICP1 ;JR ahead ; XOR A DATAENICP1: ; LD (DATAEBUFP),A ;Put back ;Calling Display here erases previous cursor ; CALL DATAEBDSP ;Display data TBT778 ; LD A,(DATAEBUFP) ;Get char pointer ; CALL BLINK ;Set bit in D7 in DATAEBUF at DATAEBUFP ; RET ;*** End: DATA ENtry Incr Char Position *** ;*** Begin: DATA ENtry Incr Character *** DATAENIC: ;Incr character LD HL,DATAEBUF ;Get table address ; LD A,(DATAEBUFP) ;Get char pointer LD A,(INCCGRPCHRPC) ;Get count CALL ADDATOHL LD A,(HL) ;Get number (0,1-9,A-F) INC A ;Incr CP 16 ;Won't allow over 16 JR NZ,DATAENIC1 ;JR ahead XOR A ;Clr Reg DATAENIC1: LD (HL),A ;Put number (0,1-9,A-F) back CALL DATAEBDSP ;Display data TBT778 RET ;*** End: DATA ENtry Incr Character *** ;*** End: DATA ENTer ************************************ ;*** Begin: ReaD Syn FReQ ********************************* ; Proposed display data output RDSFRQTL: ASCII 'F1 ' ; DEFB 0FFH ; End of string (EOS) identifier (EOSI). RDSFRQ: LD HL,RDSFRQTL ;Get address of title CALL DATATODISP ;..and output to display XOR A ;Init pointer INC A ;Set to 1 LD (RDSFPTR),A ; RDSFRQ1: ;Loop dest CALL RDMDSWDAT ;Data returned in A: (SW data) = 0000 LMRE CP 00000100B ;Mode Key JP Z,MODE1CD2 ;Back to MODE select ; CP 00000001B ;Enter Key ; JP Z,RDSFRQ01 ;to ... CP 00000010B ;Right Key CALL Z,RDSFRQIP ;Incr pointer CP 00001000B ;Left Key CALL Z,RDSFRQDP ;Decr pointer LD A,(SYNDNEW) ;Inspect flag: "SYNthesizer Data NEW" flag CP 1 JP NZ,RDSFRQ2 ;If NOT set, branch ahead ;Present state: New Data from Scanner CALL RDSSTFRQ ;RD Syn STore FReQuency in RAM CALL RDSFRDSP ;Clr SYNDNEW flag and display hex freq data CALL DELAY ;..wait for a moment, then CALL RDSFRQIP ;..Incr pointer, point to next mem location RDSFRQ2: NOP EI HALT ; Wait here for int from PIO A or CTC 3 to occur ; .. created by Scanner uP sending serial data. JP RDSFRQ1 ; Returning from interrupt causes execution of this ;...instruction. ;*** End: ReaD Syn FReQ ********************************* ;*** Begin: Dummy *** RDSFRQ0T: ASCII 'OK 1' ; DEFB 0FFH ; End identifier RDSFRQ01: LD HL,RDSFRQ0T ;Get address of title CALL DATATODISP ;..and output to display RDSFRQ02: ; CP 00000010B ;Right Key ; CALL Z,RDSFRQIP ; ; CP 00001000B ;Left Key ; CALL Z,RDSFRQDP ; ; CP 00000001B ;Enter Key ; JP Z,RSDWL ;Back to Read Synth Data Wait Loop NOP EI HALT JP RDSFRQ02 ;*** End: ... *** ;*** Begin: Incr pointer *** RDSFRQIP: ;Incr pointer LD A,(RDSFPTR) ;Get CP 20 ;Won't allow over 20 JR Z,RDSFRQIP1 ;JR ahead INC A ;Incr JR RDSFRQIP1 ;Join below ... ;*** End: Incr pointer *** ;*** Begin: Decr pointer *** RDSFRQDP: ;Decr pointer LD A,(RDSFPTR) ;Get ; CP 1 ;Won't allow under 1 CP 0 ;Won't allow under 0 TBT763 JR Z,RDSFRQIP1 ;JR ahead DEC A ;Decr RDSFRQIP1: ;****JR dest for Incr/Decr pointer LD (RDSFPTR),A ;Save for use later LD (STCHFPMX),A ;SeTup CHannel Freq Pointer ToP value CALL CNVINTASC ; Convert Reg A to ASCII in Reg A LD (ASCDSPC2),A ; Left inner char LD A,F_UCA ; LD (ASCDSPC3),A ; Left most char LD A,SP_ASC ; LD (ASCDSPC1),A ; Right inner Char LD A,SP_ASC ; LD (ASCDSPC0),A ; Right-most Char RET ;*** End: Incr/Decr pointer *** ;*** Begin: RSD Store Freq *** ; ; Subtract base freq from freq read from scanner then store in list at pointer ; ; McKinney: ; Base freq SYNBASEL EQU 047H ;Syn base freq - Low byte ; SYNBASEH EQU 083H ;.. high byte ; Plano: ; Base freq SYNBASEL EQU 0CEH ;Syn base freq - Low byte ; SYNBASEH EQU 082H ;.. high byte ; ; Addr of destination table: STCHFRQLRA: DEFB 0D6H ;Ch 1 - low byte ; ; ... + 1 high byte ; RDSSTFRQ: LD HL,STCHFRQLRA ;Get addr of SeTup CHannel FReQ List ... table ; .. 1st two bytes are SYNBASEX bytes LD A,(RDSFPTR) ;Get ReaD Synth Freq PoinTeR CP 0 JR Z,RDSSTFRQ1 ;Go xfer to SYNBASEX RAM LD C,(HL) ;Get SYNBASEL constant INC HL LD B,(HL) ;Get SYNBASEH constant DEC HL ;Point back to beginning of table XOR A ;Clr A LD D,A ;... and D (for DE register addition below) ;Create pointer in HL into table LD A,(RDSFPTR) ;Get ReaD Synth Freq PoinTeR ;... range = 1-20 ; SUB 1 ;Make range = 0-19 TBT763 SLA A ;Shift to Mult by 2 ... SLA A ;... again for total of 4 LD E,A ;... and Place into lower half of DE pair ADD HL,DE ;Sum to create pointer in HL into table LD A,(SYNRDNDV0) ;Get N divisor low byte LSH ; SUB SYNBASEL ;047H = Syn base freq, Low byte *used w/EQU* SUB C ;0XXH = Syn base freq, Low byte LD (HL),A ;Put into low byte position INC HL ;Point to high byte LD A,(SYNRDNDV1) ;Get N divisor high byte MSH ; SBC A,SYNBASEH ;083H = .. high byte SBC A,B ;0XXH = .. high byte LD (HL),A ;Put into high byte position INC HL ;Point to shift bit posn ;Transfer the Shift bit to table in RAM TBT762 LD A,(SYNRDSHFT) ;Get shift bit ; Commented out below in TBT776 - planning to invert in driver instead. ; XOR 001H ;Invert it for drive circuit in BC760XLT LD (HL),A ;Put into table RET RDSSTFRQ1: LD A,(SYNRDNDV0) ;Get N divisor low byte LSH SUB 090H ;10 MHz offset LSH LD (HL),A INC HL LD A,(SYNRDNDV1) ;Get N divisor hi byte MSH SBC A,001H ;10 MHz offset MSH LD (HL),A ; Get SYN FS bit LD A,(SYNRDSHFT) ;Save shift bit LD (SYNFSHFTRA),A RET ;*** End: RSD Store Freq *** ;*** Begin: Freq display *** ; ASCDSPC0 EQU 2004H ; ASCii DiSPlay char 00 right-most ; ASCDSPC1 EQU 2005H ; ASCii DiSPlay char 01 ; ASCDSPC2 EQU 2006H ; ASCii DiSPlay char 02 ; ASCDSPC3 EQU 2007H ; ASCii DiSPlay char 03 left-most RDSFRDSP: ;Display nter XOR A LD (SYNDNEW),A ;Clr SYN Data NEW flag, set in Syn Dat read LD A,(SYNRDNDV1) ;Get N divisor high byte MSH AND 11110000B RRCA RRCA RRCA RRCA CALL CNVINTASC ; Convert Reg A to ASCII in Reg A LD (ASCDSPC3),A ; LD A,(SYNRDNDV1) ; N divisor high byte LSH AND 00001111B CALL CNVINTASC ; Convert Reg A to ASCII LD (ASCDSPC2),A ; LD A,(SYNRDNDV0) ;Get N divisor low byte MSH AND 11110000B RRCA RRCA RRCA RRCA CALL CNVINTASC ; Convert Reg A to ASCII LD (ASCDSPC1),A ; LD A,(SYNRDNDV0) ; N divisor low byte LSH AND 00001111B CALL CNVINTASC ; Convert Reg A to ASCII LD (ASCDSPC0),A ; RDSFRDSP1: ;Display RET ;*** End: Freq display *** ;*** End: ReaD Syn data FReQ ************************* ;*** Begin: DATA TO DISPlay *********************** ; ; Input1: ; HL - Address of ASCII string to be output ; ; Input2: ; B - Count of ASCII characters to output ; HL - Address as above ; ; Internal: ; A - GP ; B - Loop variable ; DE - Points to Display address (used internally here) ; DATATODISP: DATATODISP1: ; PUSH DE LD A,4 ;Count.. LD B,A ;..count variable into Reg B LD DE,ASCDSPC3 ;ASCii DiSPlay char 03, Start w/left-most DATATODISP2: ;Input 2 and Loop dest LD A,(HL) ;Get data item LD (DE),A ;Output to Display INC HL ;Point to next item DEC DE ;Decr from 02007H to 02006H, etc DJNZ DATATODISP2 ;Loop from here ; POP DE RET ;*** End: DISPlay Rom Data OUTput ************************* ;*** Begin: PIO A Set up TRacK ********************************* ; ; Note: May have to disable CTC 3 ints as well in this routine. ; ; ; Set up PIO A for interrupt service of Trunk Data from Zero Xing det ; 1) Load INTCB (INTerrupt Control Byte), set for OR, POSitive edge ; 2) and MASKCB (MASK Control Byte) masking off SYN CLK (Synthesizer) ; enabling SC (Setup Channel) Pos edge triggering. ; ; PIO A Bit defs: ; 7 6 5 4 3 2 1 0 ; Spare Spare Mode Shift Enable Data Clock Trunk ; PIOASUTRK: ; Bit Use Bit Use ; INT EN--||-- AND/OR 7 INT EN 3 0--|Specifies ; |||-High/Low 6 AND/OR 2 1--|INTerrupt ; ||||-Mask follows 5 High/Low 1 1--|Control ; ||||ssss 4 Mask Follows 0 1--|Byte ; 76543210 LD A,10110111B ; INTCB - Mask Byte (bit 4 set) must follow OUT (PIOAC),A ; 76543210 ; PIO-A I/O pin LD A,11111110B ; MASKCB - "0" Selects Setup Ch to gen ints OUT (PIOAC),A RET ;*** End: PIO A Set up TRacKeR ********************************* ;*** Begin: INCRement Setup Channel PoinTeR ******************** ; Action: ; Increment SeTup CHannel Frequency PoinTeR ; Resets HSSYNAB flag ; Set GOTOSC flag ; INCRSCPTR: ; ;The compare value STCHFPMX is based on highest CH number TBT764 ;entered, defaulting to a value loaded from ROM LD A,(STCHFPMX) ;Get SeTup CHannel Freq Pointer ToP max val INC A ;.. add 1 ** not used with Carry bit ** LD B,A ;Into Reg to be compared to below LD A,(STCHFPTR) ;Get pointer from RAM INC A ;..Bump it up, count = 1 --> 5 or ... CP B ;Compare JR NZ,INCRSCPTR1 ;If not equal, jump ; JR C,INCRSCPTR1 ; .. C=1 if ACC 5 ; CP 6 ;Greater than 5 ... ; JP NZ,INCRSCPTR1 ;If not, jump ; XOR A ; count = 6, so ... ; INC A ; set to 1 TBT763 INCRSCPTR1: LD (STCHFPTR),A ;...New or Reset count XOR A ; LD (HSSYNAB),A ;...Reset flag INC A ;Set bit in Reg A LD (GOTOSC),A ;..and set GOTO Setup Channel flag RET ;*** End: INCRement Setup Channel PoinTeR ******************* ; Entry can be made to: 1) GOTOSCFPTR 2) STCHPTBC or 3) CALCOUTSYN ; ;1.0 GOTOSCFPTR: ;GOTO Frequency List Offset PoinTeR -combined sub entrance- ; Input - Nothing ; Output - All actions (2.0 - 4.0) and other subroutines below:- ; Output display data ; CLR GOTOSC flag ; 1.1 CALL HSIRSU ;2.0 STCHPTBC: Setup Channel frequency Pointer To BC reg pair ; Input - RAM var STCHFPTR, CHannel number in the range of ; (for Allen/McKinney system) 0 to 4. ; (for Allen/McKinney system) 1 to 5. TBT763 ; Output - Pointer in BC (to an address) ; Action: Develop a pointer in reg pair 'BC' to the Frequency (offset) list ;3.0 CALCOUTSYN: ;Calc Synthesizer Freq ; Input - BC, pointer to FREQUENCY OFFSET pair ; Output - SYNFREQL and SYNFREQH, to be output by SYNSERBC1 rout to scanner ; Action: CALL SYNSERBC1 ;SYN SERial data BearCat type 1 ; 3.1 CALL SYNSERBC1 ; Inputs - SYNFREQL and SYNFREQH bytes in RAM ; Output - Send data to the scanner's Synthesizer with CALLs to ; SERBYOUT SERBIOUT STRBEN and SYNFSOUT ;4.0 Set MUTE true (high) ; GOTOSCTL: ;1234 ASCII ' ' ; 4 spaces GOTOSCFPTR: ;Combined subroutine entrance LD HL,GOTOSCTL ;Get title CALL DATATODISP XOR A LD (GOTOSC),A ;CLR flag CALL HSIRSU ; Set up HS Int Routine programming ; CALL LSIRSU ; Set up LS Int Routine programming ; ;*** Begin: Develop Freq-offset Pointer ********************* ; Given item number of offset freq in list stored in STCHFPTR, ; Develop a pointer to the Frequency offset list in Register pair 'BC' ; ; Input - STCHFPTR, Item number (or CH number) ; For Allen/McKinney system, 0-4 ; For Allen/McKinney system, 1-5 TBT763 ; Output - Pointer in BC (to an address in ROM) ; STCHPTBC: ;SeTup CHannel frequency Pointer To BC reg pair LD A,(STCHFPTR) ; Get FREQ List Offset PoinTeR SLA A ; Double the pointer... SLA A ; Quadruple the pointer: 4 bytes per freq ; LD BC,STCHFRQLS ; Get freq list starting address in ROM LD BC,STCHFRQLRA ; Get freq list starting address in RAM ADD C ; Add Low byte of pointer to Reg A LD (DIAG00),A ; ** Diagnostic aid ** LD C,A ; Replace in Reg C LD A,0 ; LD 0 in Reg A - won't affect carry flag ADC A,B ; Add carry LD (DIAG01),A ; * Diagnostic aid * LD B,A ; Replace ... pointer now in BC ;End: Setup CHannel frequency Pointer To BC reg pair ;*** Begin: Calc Synthesizer Freq ************************* ; Calc actual synthesizer freq given: ; ; Input - Pointer, 'BC' register pair, pointing to FREQUENCY OFFSET pair ; Low/High bytes in either: ; 1) Setup Channel table or ; 2) SYNthesizer BASe freq Low/High bytes. ; ; Output - RAM bytes SYNFREQL and SYNFREQH (SYNthesizer FREQuency Low/High) ; to be output by SYNSERBC1 routine to scanner's synthesizer. ; ;SYNBASEL: DEFB 047H ;Syn base freq - Low byte ;SYNBASEH: DEFB 083H ; .. high byte ; CALCOUTSYN: XOR A LD (GOTOVC),A ;Rst Flag LD A,(SYNBASEL) ;Get Base freq low byte LD E,A ;Save for use below LD A,(SYNBASEH) ;..high byte LD D,A LD A,(BC) ; Get Freq offset low byte pointed to by BC LD (DIAG02),A ; * Diagnostic aid * ; ADD A,047H ; Add the BASE Freq to the ACCUM (Reg A) ; ADD A,0CEH ; Add the BASE Freq to the ACCUM (Reg A) ADD A,E ; Add the BASE Freq to the ACCUM (Reg A) LD (SYNFREQL),A ; Save low byte for output to SYN IC INC BC ; Point to high byte ... LD A,(BC) ; .. Get Freq offset high byte LD (DIAG03),A ; * Diagnostic aid * ; ADC A,083H ; .. Add high byte along with carry bit ; ADC A,082H ; .. Add high byte along with carry bit ADC A,D ; .. Add high byte along with carry bit LD (SYNFREQH),A ; Save high byte for output to synthesizer. ; Transfer frequency shift bit to RAM INC BC ; Point to shift byte ... LD A,(BC) ; .. Get shift bit contained in byte ; XOR 001H ; .. invert it TBT766 LD (SYNFSHFT),A ; .. save it for SYNSERBC1 routine LD (DIAG04),A ; * Diagnostic aid * ;*** End: Calc Synthesizer Freq ************************* ; Send data to the scanner's Synthesizer CALL SYNSERBC1 ;SYN SERial data BearCat type 1 ;..Outputs bytes in RAM to scanner synthesizer LD A,(OLDSDATA) ;Get old serial data output status OR 00010000B ;Set MUTE true (high) LD (OLDSDATA),A ;Update OLD Serial Data TBT733 OUT (PIOBD),A ;..And output to PIO B RET ;*** End: Combined subroutines ********************* ; ** Note: This origin cannot be changed without blowing a new high mem PROM ** ORG 0600H C0SOTBL1: ;Ctc 0 Sync Operations TaBLe 1 ; Was: JP C0OEXT ; 0 no specified action ** 1st action ** NOP ; .. NOP for spacing JP C0OXFER ; 1 go XOR, xfer data ** 2nd action ** NOP ; JP C0ONBGD ; 2 OSW w/no Bck gnd wrds ** 3rd action ** ; JP C0OEXT ; 5 Exit NOP ; ; JP C0OACOM ; 3 goto OSW Addr COMpare JP C0ODCOM ; 3 goto OSW Data COMpare NOP ; ; JP C0OEXT ; 4 Exit JP C0OACOM ; 3 goto OSW Addr COMpare NOP ; JP C0OEXT ; 5 Exit ; JP C0ONBGD ; 2 OSW w/no Bck gnd wrds NOP ; JP C0OCOSWC ; 6 go CLR OSWCST NOP ; JP C0OEXT ; 7 Exit ** Last action ** NOP ; ;*** End: Operations select ********************* ;*** Begin: **************** C0OSYN: JP C0OEXT ;End of Sync-action select ;*** End: ****************** ;*** Begin: Ctc 0 Osw Data COMpare ******************* ; OSWXOUT: ; +0 A0 - A7 Left half "Address" byte ; +1 A8 - A15 Right half "Address" ; +2 C2 - C9 Data/Freq, right eight bits ; +3 0 0 0 T 0 0 C0 C1 Type, Left 2 Data/Freq MSB's ; C0ODCOM: ; OSW Data COMpare LD A,(OSWXOUT+3) ;+3 = 0 0 0 T 0 0 C0 C1 Type, Data/Freq MSB ; 7 6 5 4 3 2 1 0 BIT 4,A ;Bit 4 in Reg A: Individual Call Bit JP NZ,C0ODCOM1 ;If bit NOT set, Z flag is set ;Present state: Individual call bit NOT set LD BC,10 ;Load byte count to be decremented ; LD BC,(OSWDABC) ;Load OSW DAta Byte Count to be decremented LD HL,FRQLISTRRH ;Get list address *Rom* Right Half C0ODCOM2: ;Loop destination f/Left Half LD A,(OSWXOUT+2) ;+2 C2 - C9 Data/Freq, right eight bits CPIR ;'Z' flag set when A=(HL) (21,16) JP Z,C0ODCLH ;A=(HL) so go check left half. (10) JP C0ODCOM1 ; ;*** *********** C0ODCLH: ;Left half of OSW Data/Freq LD IY,FRQLISTRLH ;Get list address *Rom* Left Half (14) ADD IY,BC ;Create pointer in IY (15) ;Note: This creates a pointer that ;starts at the TOP and works down. LD A,(OSWXOUT+3) ;+3 0 0 0 T 0 0 C0 C1 Type, Left 2 F MSB's CP A,(IY) ;Compare (19) JP Z,C0ODCOM3 ;Jump if match (10) ;Check BC, if BC .NE. 0 jump back LD A,C ;Get count (4) CP 0 ;Dec'd to zero? (7) JP NZ,C0ODCOM2 ;No, search again w/ct in BC (10) JP C0ODCOM1 ; C0ODCOM3: ;Present state: Freq match found ; LD A,10 ;Create channel number in Reg A LD A,9 ;Create offset into table SUB A,C ;Adjust count LD IY,FRQLISTRCOR ;Get list address *Rom* Left Half (14) SLA A ;Double LD C,A ADD IY,BC ;Create pointer in IY (15) LD A,(IY) LD (OSWXOUT+2),A ;+2 C2 - C9 Data/Freq, right eight bits LD A,(IY+1) LD (OSWXOUT+3),A ;+3 0 0 0 T 0 0 C0 C1 Type, Left 2 F MSB's XOR A ;Clr A INC A ;Set A and LD (FRQDATGD),A ;.. set FReQ DATa GooD flag JP C0OEXT ;End of Sync-action select C0ODCOM1: ;Present state: Individual Call bit found XOR A LD (FRQDATGD),A ;Clr FReQ DATa GooD flag JP C0OEXT ;End ;*** End: Ctc 0 Osw Data COMpare ******************* ;*** Begin: Ctc 0 Osw Addr COMpare ******************* ; C0OACOM: LD A,(FRQDATGD) ;Clr FReQuency DATa GooD flag CP 1 JP NZ,C0OEXT LD BC,16 ;Load byte count to be decremented TBT791 ; LD BC,(OSWADBC) ;Load OSW ADdr Byte Count to be decremented LD HL,CGLISTRH ;Get list address Right Half C0OACOM1: ;Loop destination f/Left Half LD A,(OSWXOUT+1) ;+1 = A8 - A15 Right half "Address" byte C0OACOM2: ;Loop destination f/Right Half CPIR ;'Z' flag set when A=(HL) (21,16) JP Z,C0OACLH ;A=(HL) so go check left half.(10) JP C0OEXT ;No matchs, exit ;*** *********** C0OACLH: ;Left half of OSW addr LD IY,CGLISTLH ;Get list address Left Half (14) ADD IY,BC ;Create pointer in IY (15) ;Note: This creates a pointer that ;starts at the TOP and works down. LD A,(OSWXOUT) ; = A0 - A7 Left half "Address" byte CP A,(IY) ;Compare (19) JP Z,CT0ADDRM0 ;Jump if match (10) ;Check BC, if BC .NE. 0 jump back LD A,C ;Get count (4) CP 0 ;Dec'd to zero? (7) JP NZ,C0OACOM1 ;No, search again w/ct in BC (10) JP C0OEXT ;Search ended, exit ;*** End: Ctc 0 Osw Addr COMpare ******************* ;*** Begin: 4-Char ASCII Display output ************ ; CT0ADDRM0: LD HL,CGLISTCHL ;Call Group LIST rom CHanneL addrs LD A,16-1 ;Always one less than value in BC ; LD A,(OSWADBC) ;Load OSW ADdr Byte Count to be decremented ; DEC A ;Reduce by 1 (if necc) SUB C ;Determine offset; MAX_cnt - counted SLA A ;Mult by 2 SLA A ;.. again for a total of 4 CALL ADDATOHL CALL DATATODISP XOR A INC A LD (GOTOVC),A ;Set the Goto Voice Channel flag JP C0OEXT ; to exit ;*** End: 4-Char ASCII Display output *********************** ;*** Begin: C0 Osw w/No Back GrounD words ******************** ; ; ** Diagnostic aid ** ; ; The following outputs 'screened' OSW address information to a block of ; memory locations to allow the logic analyzer to view "purified" OSW addr ; info with out distracting background or System ID words being seen. ; ; ; Screen for any background or System ID words. If any are present then ; skip transferring these from OSWXOUT to OSWSOUT. ; C0ONBGD: ; Data output without background words LD A,(OSWXOUT) ; +0 A0 - A7 Left half "Address" byte ; CP 01FH ; Belive this to be System ID (1Fxx) CP 00BH ; JP Z,C0ONBGD12 ; Chk other half if match CP 030H ; Ignore this too JP Z,C0OEXT ; Exit - Background word found CP 01FH ; Ignore system ID, too JP Z,C0OEXT ; Exit - Background word found CP 02BH ; Ignore this too JP Z,C0OEXT ; Exit - Background word found CP 0B2H ; Ignore this too JP Z,C0OEXT ; Exit - Background word found CP 0BAH ; Ignore this too JP Z,C0OEXT ; Exit - Background word found CP 02AH ; Ignore this too JP Z,C0OEXT ; Exit - Background word found CP 0C6H ; Ignore this too JP Z,C0OEXT ; Exit - Background word found ; Chk next pattern ... CP 040H ; Left half Background word (0B19) ; JP Z,C0OEXT ; Exit - Background word found JP NZ,C0ONBGD20 ; jump to data output if no match C0ONBGD11: ; LD A,(OSWXOUT+1) ; +1 A8 - A15 Right half "Address" ; CP 040H ; Right half Background word JP Z,C0OEXT ; Exit - Background word found C0ONBGD12: LD A,(OSWXOUT+1) ; +1 A8 - A15 Right half "Address" CP 019H JP Z,C0OEXT ; Exit - A "background word" was found ; ; Write screened OSW Setup Channel data to an otherwise unused RAM ; location so that it can be seen by the Logic Analyzer ; C0ONBGD20: ; LD A,(FRQDATGD) ;Examine FReq DATa GooD flag ; CP 1 ; JP NZ,C0OEXT LD A,(OSWXOUT) ;Base adrs for assembled OSW LD (OSWSOUT),A LD A,(OSWXOUT+1) LD (OSWSOUT+1),A LD A,(OSWXOUT+3) ;was +2 LD (OSWSOUT+2),A LD A,(OSWXOUT+2) ;was +3 LD (OSWSOUT+3),A JP C0OEXT ;Exit ;*** End: C0 Osw w/No Back GrounD words ************************* ;*** CTC 0 XFER routine *************************** ; ; 1) Auto-Sync sequence XOR on data assembled in Outbound Status Word ; ConStruction Table then ; ; 2) Move the data into the Outbound Status Word Xfer OUTput array for use ; by ; C0OXFER: ;Xfer data from OSWCST to OSWXOUT LD A,(OSWCST) ;Base adrs for assembled OSW XOR 11001100B ;Modulo-2 Addition for Auto-Sync Sequence LD (OSWXOUT),A ;OSW ADDRESS MS left half "Address" byte A0-A7 LD A,(OSWCST+1) ;OSW Base adrs + offset XOR 00111000B ;Mod-2 ASSQ LD (OSWXOUT+1),A ;OSW ADDRESS LS right half "Address" byte A8-A16 LD A,(OSWCST+2) ;OSW Base adrs + offset AND 00010011B ;Mask (Call Type: 0001, 2 Stat MSB's: 0011) ; XOR 00000000B ;Mod-2 AS SEQ (all zeroes for CT, 2 MSB's) ; LD (OSWXOUT+2),A ;OSW Call Type and two Status/Freq/Dat bits ; For use by Syn Ser Data routine - put high order byte last LD (OSWXOUT+3),A ;OSW Call Type and two Status/Freq/Dat bits LD A,(OSWCST+3) ;OSW Base adrs + offset XOR 11010101B ;Modulo-2 addition for Auto-Sync Sequence ; LD (OSWXOUT+3),A ;OSW Data/Freq right eight bits C2-C9 ; For use by Syn Ser Data routine - put low order byte 1st LD (OSWXOUT+2),A ;OSW Data/Freq right eight bits C2-C9 JP C0OEXT ;*********************************************************** ;** Begin: ************************ ; Clear the array that the incoming OSW bits are assembled into. ; -Necessary since only 1's are written into memory C0OCOSWC: ;Clr OSW Const array XOR A ;CLR Reg A LD (OSWCST),A ;Base adrs for assembled OSW LD (OSWCST+1),A ; LD (OSWCST+2),A ; LD (OSWCST+3),A ; ; JP C0OEXT ; TBT740 ';' out ;*** End: ********************************************** ;*** Begin: ************************ TBT740 ; Read mode switch: ; Write out to B to insure line high ; Read A, save in memory location. C0RDMDSW: ;C0 ReaD MoDe SWitch LD A,(OLDSDATA) ; Get old data bound for PIO B ; 76543210 ; 01100000 ; SW Out x11x xxxx ; 76543210 ; Set SW Out AND 10111111B ; Clr bit 6 OR 00100000B ; Set bit 5 true (high) OUT (PIOBD),A ; Output to PIO B IN A,(PIOAD) ; Read PIO A, one of three bits may be high... ; 76543210B AND 11100000B ; Mask off all but Keyboard Switch INputs RLC A ;Rotate left: 1110 0000 to 1100 0001 RLC A ;Rotate left: 1100 0001 to 1000 0011 RLC A ;Rotate left: 1000 0011 to 0000 0111 CP 00000000B ; ** Diagnostic aid ** JP Z,C0RDMDSW1 LD (C0HSSWDT),A ;MoDe SWitch DATa C0RDMDSW1: JP C0OEXT ; ;*** End: ********************************************** ;*** Begin: Convert integer to ASCII ******************** ; Input: Reg A, containing 0-F (hex integer) ; Output: Reg A, an ASCII char ; Regs- ; used: B ; affected: none CNVINTASC: ; PUSH BC LD B,030H ;Base hex number for ASCII 0-9 *default CP 10 ; ACC::OP JR C,CNVINTASC1 ; .. C=1 if ACC 7 thru 4 ;.. Left=7 6 5 Right=4 LD C,A ;Replace LD A,(BC) ;Read char from display OR 080H ;Set Blink current char LD (BC),A ;Write char to display POP BC RET ;*** End: BLINK *** ;*** Begin: UNBLINK character *** ; Calling format: ; LD A,x ;Point to char 0-L 1 2 3-R ; CALL UNBLINK UNBLINK: ;Resets bit in D7 in display character PUSH BC LD C,A ;Save LD B,020H ;Get Display MSH addrs LD A,7 ;..LSH addrs SUB C ;Offset 7 by char_pointer_amount => 7 thru 4 ;.. Left=7 6 5 Right=4 LD C,A ;Replace LD A,(BC) ;Read char from display AND 07FH ;Strip bit in current char LD (BC),A ;Write char to display POP BC RET ;*** End: UNBLINK *** ;*** Begin: ReaD MoDe SWitch DATa ******************** ; Prevent data in MDSWDAT1 from causing a continuous loop by: ; 1. Clearing MDSWDAT1 ; 2. Passing back data in Reg A RDMDSWDAT: ; PUSH AF ; PUSH BC LD A,(MDSWDAT1) ;Get key data LD B,A ;Temp copy XOR A LD (MDSWDAT1),A ;Clr data - any subsequent reads by other ; ; ..routines will result in null data. LD A,B ;Get Temp copy back ; POP AF ; POP BC RET ;*** End: ReaD MoDe SWitch DATa ******************** ;*** Begin: DATA Entry Buffer to DiSPlay ********************** ; Outputs the HEX data in "DATA Entry Buffer" to the ASCII display ; ; Input: In the future, perhaps the addrs of a buffer in the HL pair ; Output: ASCII Data to Display (memory locations 2007-2004) ; Regs used: A, B, DE, HL ; DATAEBDSP: ;DATA Enter Buffer to DiSPlay LD HL,DATAEBUF ;Get buffer addrs in RAM LD DE,02007H ;Load addrs of Display LD B,4 ;4 chars DATAEBDSP1: ;Loop dest LD A,(HL) ;Get Hex integer in buffer ;CNVINTASC preserves all regs exc F CALL CNVINTASC ;I/O: Reg A, IN=0-F, OUT=ASCII equivalent LD (DE),A ;Write ASCII char to display INC HL DEC DE DJNZ DATAEBDSP1 ;Decr Reg B, jump on Not Zero RET ;*** End: ********************* ;*** Begin: DELAY **** ; Reg not saved: IX DELAY: PUSH BC PUSH DE LD IX,0FC00H ;Init for outer loop LD DE,1 DELAY1: LD B,255 ;Inner loop DJNZ $ ADD IX,DE JP NC,DELAY1 POP BC POP DE RET ;*** End: DELAY ******** ;*** Begin: SUBtract A FRom HL ********** SUBAFRHL: PUSH BC ;Preserve BC pair LD C,A ;Put subtractor into Low Half XOR A ;Clr: A and CY_bit LD B,A ;Clr high byte in B SBC HL,BC ;HL=HL-BC-CY_bit POP BC ;Restore BC pair RET ;*** End ************* ;*** Begin: Subroutines to reside in upper 2K EPROM ORG 0800H ;*** Begin: Read Synthesizer Data Interrupt Set Up **************** ; ; Set up PIO A for interrupt service of SYNthesizer CLK from Rcvr ; 1) Load INTCB (INTerrupt Control Byte), set for OR, POSitive edge ; 2) and MASKCB (MASK Control Byte) masking off SC (Setup Channel) Data ; and enabling CLOCK from receiver's processor for positive edge ; triggering to read data which is normally sent to receiver's LO ; requency synthesizer. ; ; Set up CTC 3 ; 3) Set for a count of 1, positive edge trigger ; 4) Place interrupt service routine address into RAM at CTC 3 Int Vec addrs. ; ; ** Note: Z-80 PIO requires a change in the LOGIC OR'd inputs from all ; enabled (unmasked inputs) from a false state to a true state before ; an interrupt can be generated since the result of a logic OR of a false ; state and a true state is a true state: FALSE + TRUE = TRUE. ; ; PIO A Bit defs: ; 7 6 5 4 3 2 1 0 ; Spare Spare Mode Shift Enable Data Clock Trunk ; RSDISU: ; ;PIO A: Setup for -Read Synth Data- Int service ; Bit Use Bit Use ; INT EN--||-- AND/OR 7 INT EN 3 0--|Specifies ; |||-High/Low 6 AND/OR 2 1--|INTerrupt ; ||||-Mask follows 5 High/Low 1 1--|Control ; ||||ssss 4 Mask Follows 0 1--|Byte ; ;PIO A 76543210 LD A,10110111B ; INTCB - Mask Byte (bit 4 set) must follow OUT (PIOAC),A ; 76543210 ; PIO-A I/O pin LD A,11111101B ; MASKCB - "0" Selects SYN CLK to gen ints OUT (PIOAC),A LD HL,PIOAIRSD ;Get addrs of PIO A Int Read Synth Data rout LD (PIOAIV),HL ;..and load into PIO A Int Vector ; ;PIO B None ; NOP ;CTC 0: Disable Interrupts LD A,CTCDIHS ;CTC Disable Ints High Speed OUT (CT0),A ;CTC 1: None ; NOP ;CTC 2: None ; NOP ;CTC 3: Synthesizer ENAble line monitor from Rcvr LD A,CTCCMEILP ;CTC 3 Counter Mode, En Ints, Load, Pos edge OUT (CT3),A ; LD A,1 ;Count of 1 (one) OUT (CT3),A ;Load into CTC LD HL,CT3IRSD ;Get addrs of CT 3 Interrupt Read Syn Data rou LD (CT3IV),HL ;.. and load into CTC 3 Int Vector RET ;*** End: Read Synthesizer Data Interupt Set Up **************** ;*** Begin: PIO A Interrupt Read rcvr Synthesizer Data **************** ; ; Respond to Synthesizer CLK positive transitions and grab Data bit. ; The ENable line is monitored under interrupt control by CTC 3. ; ; Action: ; Read incoming serial data bit when CLK occurs and put it into it's own ; memory location, SYNRDRN. Shift all subsequent data THROUGH this single ; bit position and into two contigous bytes. ; ; This results in 16 bits existing in two bytes and the last bit existing ; into it's own byte. The first 16 bits represent the /R number. The lone ; 17th bit in the logic 1 state indicates /R (a logic 0 indicates /N). ; ; Normally the /R is sent first followed by /N. In any case a positive pulse ; on the ENable line strobes data into one of the two holding registers (/R or ; /N) depending on the logic level of the 17th bit. ; ; The next 16 bits (17-33) are the /N number, followed by the last bit (34) ; set to logic 0 and another pulse on the ENable line. ; ; ;SYNthesizer Read Data Ref or N ;SYNRDRN: DEFB 0 ;Data type bit, "R"ef or "N" ;SYNRD0: DEFB 0 ;SYN Read Data, low byte ;SYNRD1: DEFB 0 ; ... high byte ; ;SYNRDREF0: DEFB 0 ;Ref divisor, low byte ;SYNRDREF1: DEFB 0 ; ... high byte ; ;SYNRDNDV0: DEFB 0 ;N divisor, low byte ;SYNRDNDV1: DEFB 0 ; ... high byte ; ; Bit defs: |Trunk Data | ; |---Mode---|---- From Scanner/Rcvr ----|From SCF & | ; | Switch | Processor |Comparator | ; | | --- ------ ; | | | | ; 7 | 6 5 | 4 | 3 2 1 | 0 | <---Bit position ; Sp | Sw1 Sw0 | Shift | Enable Data Clock| TDATA| <---Signal ; - Low Low N/A | Low - High - <---Normal level ; - Log Log Logic | Pos pls - Neg pls - <---Characteristics ; - N/A N/A N/A | 70 uS - 25 uS - <---Width ; - - - - | CTC 3 - PIOA - <---Int Service ; PIOAIRSD: ;PIO A Read Syn Data routine PUSH AF PUSH BC IN A,(PIOAD) ; Reading PIO A immediately after arriving AND 04H ; Mask off all bits except SYN Ser. Data LD B,A ; Save bit for the moment LD A,(SYNRD0) ;Get MSBit in low byte .. AND 80H ;..mask off all except MSBit RLC A ;..put it into LSBit position LD C,A ;..save it temporarily ; LD A,(SYNRD1) ;Get high byte .. SLA A ;..shift left, ditching MSBit... OR C ;..Logical OR bit from low byte... LD (SYNRD1),A ;..and put it back LD A,(SYNRDRN) ;Get bit from SYNRDRN AND 01H ;Mask off LD C,A ;..save ; LD A,(SYNRD0) ;Get low byte .. SLA A ;..Shift left OR C ;..Logical OR bit from RDRN byte into LSB LD (SYNRD0),A ;..and put it back LD A,B ;Get serial bit we read: xxxx 0100 LD (PIOASSD),A ;Output data bit ** Diagnostic aid ** SRA A ;Shift right: 0100 to 0010 SRA A ;to 0001 LD (SYNRDRN),A ;..and finally save it. PIOAIRSDX: ; Exit POP BC POP AF EI RETI ; Exit 1 ;*** End: PIO A Rcvr Synthesizer Data routine ****************** ;*** Begin: CTc 3 Interrupt Read Synthesizer Data routine **************** ; ; Revised 11-14-92 TBT753 ; Positive transitions of the ENable line from the receiver are monitored ; by this routine. The occurance of the positively pulsed ENable line ; signals that data is to be loaded into either the 16 bit divide by R ; (Reference register) or the 16 bit divide by N Register depending on the ; last (17th bit) in each series. ; CT3IRSD: ;CT 3 Interrupt Read Syn Data PUSH AF ;Preserve A and Flag reg PUSH BC ; ** Diagnostic aid ** ; IN A,(PIOAD) ; LD B,A ;Temp storage ; ; 76543210 ; AND 00011000B ;Mask off all but ... and "ENable" bit ; LD (PIOASEB),A ;Output it ** Diagnostic aid ** ; ** Diagnostic aid ** LD A,(SYNRDRN) ;Data type bit, "R"ef or "N" CP 0 ; JP Z,CT3IRSDN ; JP if bit was not set JR Z,CT3IRSDN ; JP if bit was not set CT3IRSDR: ;Xfer data to /R buffer LD A,(SYNRD0) LD (SYNRDREF0),A LD A,(SYNRD1) LD (SYNRDREF1),A ; JP CT3IRSDSX ;To exit JR CT3IRSDSX ;To exit CT3IRSDN: ;Xfer data to /N buffer LD A,(SYNRD0) LD (SYNRDNDV0),A LD A,(SYNRD1) LD (SYNRDNDV1),A CT3IRSDS: ;Shift bit reading IN A,(PIOAD) ; 76543210 AND 00010000B RLC A ;Rotate bit left 0001 0000 to 0010 0000 RLC A ;Rotate bit left 0010 0000 to 0100 0000 RLC A ;Rotate bit left 0100 0000 to 1000 0000 RLC A ;Rotate bit left 1000 0000 to 0000 0001 LD (SYNRDSHFT),A ;Save shift bit XOR A ; INC A LD (SYNDNEW),A ;Set the SYN Data NEW flag ;Exit CT3IRSDSX: ;Shift bit POP BC POP AF EI RETI ; Exit 1 ;*** End: CT 3 Interrupt Read Synthesizer Data routine **************** ;*** Begin: CTc 1 Keyboard (KYB) Timer Int routine ******************* ; ; Switch data: 0000 LMRE ; ; The Track routine reads the Mode SW Kybd, if active MODE 1 code is entered. ; Once out of the Track mode the Keyboard is monitored via timed interrupts ; from CTC 1 in this routine. ; CT1KTI: ;CTC 1 Keyb Timer Interrupt routine PUSH AF PUSH BC EI ; Try for TBT755 ;Read left top and bottom keys on PIO A with PIO B bit 5 high LD A,(OLDSDATA) ; Get old data bound for PIO B ; 7654 3210 ; 01100000 ; SW Out x01x xxxx ; 76543210 ; Set SW Out AND 10111111B ; Clr bit 6 OR 00100000B ; Set bit 5 true (high) OUT (PIOBD),A ; Output to PIO B IN A,(PIOAD) ; Read PIO A, one of three bits may be high... ; 76543210B AND 01100000B ; Mask off all but Keyboard Switch INputs ; || ; | ---"Mode" .. Left two keys ; | ; ---- "<--" Key ; Rotate into position RLC A ;Rotate left: 0110 0000 to 1100 0000 RLC A ;Rotate left: 1100 0000 to 1000 0001 RLC A ;Rotate left: 1000 0001 to 0000 0011 ; Two more positions to the right RLC A ;Rotate left: 0000 0011 to 0000 0110 RLC A ;Rotate left: 0000 0110 to 0000 1100 LD B,A ;Save fast access copy ;Read right top and bottom keys on PIO A with PIO B bit 6 high LD A,(OLDSDATA) ; Get old data bound for PIO B ; 76543210 ; 01100000 ; SW Out x10x xxxx ; 76543210 ; Set SW Out AND 11011111B ; Clr bit 5 OR 01000000B ; Set bit 6 true (high) OUT (PIOBD),A IN A,(PIOAD) ; Read PIO A ; 76543210B AND 01100000B ; Look at Keyboard Switchs only ; || ; | ---"Ent" .. Right two keys ; | ; --- "-->" Key RLC A ;Rotate left: 0110 0000 to 1100 0000 RLC A ;Rotate left: 1100 0000 to 1000 0001 RLC A ;Rotate left: 1000 0001 to 0000 0011 OR B ;Combine with left two keys from above LD C,A ;Save composite in another fast access copy ;Present state: New data in Reg A, C LD A,(MDSWDAT0) ;Get old data LD B,A ;Fast access copy of old data CP C ;How does it compare with new data.. JP Z,RDMDSW00 ;If match -no change- jump ;Present state: old data doesn't match new data LD A,C ;Get new (composite) data LD (MDSWDAT0),A ;And save in MoDe SWitch DATa CP 0 ;Compare with Null data JP NZ,RDMDSW00 ;If no match -no change- jump ;Present state: old/new data don't match ; ..and now reading null data LD A,B ;Get old data LD (MDSWDAT1),A ;And save in MoDe SWitch DATa RDMDSW00: POP AF POP BC RETI ;*** End: CTc 1 Keyboard Timer Int routine ********************* ;*** Begin: CTc 0 Dummy Keyboard Int routine ******************* CT0DUM: ;CTC 0 Keyb Timer Interrupt routine NOP RETI ;*** End: CTc 0 Dummy Keyboard Int routine ********************* ; ;*** Begin: High Speed Sampling/SCF CTC Setup Routines ************ ; Program CTC, setup PIO and CTC Interrupt Service Routine (ISR) ; addresses in RAM. ; CTC 0 - Load count for HS Data sampling interrupt ; CTC 1 - Reset Keyboard sampling interval timer ; CTC 2 - Load count for Switched Capacitor Filter Clock ; CTC 3 - Reset (Rcvr Syn ENable line monitor) ; PIO A - ISR addrs in RAM for servicing PIO A ; CTC 0 - ISR addrs in RAM for servicing CTC 0 ; *CTC 1 - ISR addrs in RAM for servicing CTC 1 Disconnect Int Routine ;'*' Not in this routine HSIRSU: XOR A LD (PRVDATGD),A ;Clr so CT0AOCAM routine won't re-use old data ;..and issue a GOTOVC flag. ;Start CTC 0 - used for data sampling LD A,CTCLREHS ;High Speed data sampling rate OUT (CT0),A ; .. LD A,70 ; HS count OUT (CT0),A ; .. LD A,CTCRS ;CTC 1 Reset OUT (CT1),A ; ;Start CTC 2 - used for SCF Clock LD A,CTCLRDHS ;SCF clock for HS Data OUT (CT2),A LD A,1 ;Count of 1 (one) OUT (CT2),A ;Load into CTC LD A,CTCRS ;CTC 3 Reset OUT (CT3),A ; ;Load ISR vectors LD HL,PIOAHSIR ;PIO A High Speed Interrupt Routine LD (PIOAIV),HL LD HL,CT0HSI ;CTC 0 High Speed Interrupt routine LD (CT0IV),HL RET ;*** End: High Speed sampling/SCF CTC Setup Routines ****** ;*** Begin: Low Speed sampling/SCF CTC Setup Routines ****** ; See HSIRSU for details. LSIRSU: LD A,CTCLRELS ;Low Speed data sampling rate OUT (CT0),A ; .. LD A,104 ; .. OUT (CT0),A ; .. LD A,CTCLRDHS ;SCF clock for LS Data OUT (CT2),A LD A,18 ;Count of ... OUT (CT2),A ;Load into CTC LD HL,CT0LSI ;CTC 0 int routine vector Low Speed LD (CT0IV),HL ;Put into RAM LD HL,CT1DISINT ;CTC 1 int routine Disconnect timing LD (CT1IV),HL ;Put into RAM LD HL,PIOALSIR ;PIO A Low Speed Interrupt LD (PIOAIV),HL ;Put into RAM RET ;*** End: Low Speed sampling/SCF CTC Setup Routines ****** ;*** Begin: KeYBoard Timer Int Set Up Routines ************ ; Program CTC and CTC Interrupt Service Routine (ISR) addresses in RAM. ; CTC 0 - Reset ; CTC 1 - Load count for Keyboard sampling interval ; *CTC 2 - Load count for Clock for Switched Capacitor Filter ; *CTC 3 - Reset (Rcvr Syn ENable line monitor) ; *PIO A - ISR addrs in RAM for servicing PIO A ; CTC 0 - ISR addrs in RAM for Dummy servicing of CTC 0 ; CTC 1 - ISR addrs in RAM for servicing CTC 1 ; '*' means not at present KYBTISU: LD A,CTCRS ;CTC 0 Reset OUT (CT0),A ; LD A,PIODI ; Diasable PIO A int OUT (PIOAC),A ;Start CTC 1 - used for Keyboard sw sampling LD A,CTCLRELS ;Low Speed OUT (CT1),A ; .. LD A,200 ; count, approx 78.125 Hz or 12.8 mS OUT (CT1),A ; .. ; ;Start CTC 2 - used for SCF Clock ; LD A,CTCLRDHS ;SCF clock for HS Data ; OUT (CT2),A ; LD A,1 ;Count of 1 (one) ; OUT (CT2),A ;Load into CTC ; LD A,CTCRS ;CTC 3 Reset ; OUT (CT3),A ; ; ;Load ISR vectors ; LD HL,PIOAHSIR ;PIO A High Speed Interrupt Routine ; LD (PIOAIV),HL LD HL,CT0DUM ;CTC 0 Dummy Keyb Interrupt routine LD (CT0IV),HL LD HL,CT1KTI ;CTC 1 Keyb Timer Interrupt routine LD (CT1IV),HL RET ;*** End: KeYBoard Timer Int Set Up Routines ************** ;*** Begin: Serial I/O to BC760XLT synthesizer ************* ; ; Input: Data in RAM ; Action: Output REFFREQ0/1 bytes from RAM ; Output SYNFREQL/H bytes from RAM ; Output SYNFSHFT bit from byte in RAM ; ; Parallel PIO B ; Bit definitions: x x x MUTE SHFT EN DAT CLK ; ; Signals: ; Clock 17/34 serial data clock pulses ; Normally high ; Data 17/34 bits of serial data ; Normally low ; Enable Positive pulse - xfers data from SR to /R or /N latch ; Normally low ; Shift Logic 1 selects *downward* shift in frequency ; Set low for init ; SYNSERBC1: ;SYNthesizer Serial data BearCat type 1 NOP ; *** Reference divisor output *** LD A,(REFFREQ0) ;Get synthesizer REF freq most significant byte CALL SERBYOUT NOP LD A,(REFFREQ1) ;.. least significant byte CALL SERBYOUT NOP ;Set /R register-select bit (1) as 17th bit XOR A ;Clr A INC A ;Set LSB CALL SERBIOUT ;Output bit NOP CALL STRBEN ;move data from SR to Ref divisor latch SERDATF: ; *** Frequency divisor output *** LD A,(SYNFREQH) ;Get synthesizer freq most significant byte CALL SERBYOUT NOP LD A,(SYNFREQL) ;Get synthesizer freq least significant byte CALL SERBYOUT NOP ; Set /N register-select bit (0) as 17th bit XOR A CALL SERBIOUT ;Bit output NOP CALL STRBEN ; Output /SHFT data bit on PIO line LD A,(SYNFSHFT) ; Get "/Freq SHIFT" bit f/RAM (5 or 12.5 KHz dn) XOR 001H ; .. invert it CALL SYNFSOUT ; Output SHIFT bit plus other housekeeping chores RET ;*** End: Serial I/O to BC760XLT synthesizer ************ ;*** Begin: SERial Byte OUTput subroutine ************* ; Data byte in reg A is output: Clk line is pulsed low and ; the data from MSB through LSB is strobed into the shift register in ; the syn. ; Regs used: A going in, contains data to be output ; B counter for loop ; C fast access copy SERBYOUT: ;Move MSB (7) into bit 1 position RLCA RLCA LD C,A ;MSB to bit position 1 LD B,8 ;Init Reg B for counter operation LD A,(OLDSDATA) ;Get old data SERBYOT1: ; x x x MUTE SHFT EN DAT CLK ; State x x L x H AND 00000010B ;Let OLD Data bit through set CLK low OUT (PIOBD),A ;..output it ; x x x MUTE SHFT EN DAT CLK ; State x x L x L LD A,C ;Get new data AND 00000010B ;Let Data bit through with Clk low OUT (PIOBD),A ;..output it and make Clk low ; x x x MUTE SHFT EN DAT CLK ; Coming out x x L x L ; x x x MUTE SHFT EN DAT CLK ; Going in x x L x L OR 00000001B ;Set Clk bit high OUT (PIOBD),A ;Output with Clk going high ; x x x MUTE SHFT EN DAT CLK ; Coming out x x L x H RLC C ;Shift bits DJNZ SERBYOT1 ; Dec Reg B, jump not zero Bit Posn Rotate LD A,C ;Get data RRC A ;Undo last shift LD (OLDSDATA),A ;save for use as old serial data RET ;*** End: Serial data output routine ***************** ;*** Begin: SERial Bit OUTput subroutine ************ ; Data bit in LSB position in reg A is output: Clk line is pulsed low and ; the data bit is strobed into the shift register in the syn. ; Regs used: A going in, contains bit to be output ; SERBIOUT: ;Move Bit 0 into bit 1 position RLCA ;0 to 1 (bit 1 is Data bit position) LD C,A ;Fast access copy LD A,(OLDSDATA) ;Get old data ; x x x MUTE SHFT EN DAT CLK ; State x x L x H AND 00000010B ;Let OLD Data bit through set CLK low OUT (PIOBD),A ;..output it ; x x x MUTE SHFT EN DAT CLK ; State x x L x L LD A,C ;Get new data AND 00000010B ;Let Data bit through with Clk low OUT (PIOBD),A ;..output it and make Clk low ; x x x MUTE SHFT EN DAT CLK ; Coming out x x L x L ; x x x MUTE SHFT EN DAT CLK ; Going in x x L x L OR 00000001B ;Set Clk bit high OUT (PIOBD),A ;Output with Clk going high ; x x x MUTE SHFT EN DAT CLK ; Coming out x x L x H LD (OLDSDATA),A ;save for use as old serial data RET ;*** End: Serial data output routine ************* ;*** Begin: STRoBe ENable line subroutine ******** ; The ENable line is pulsed high ; Regs used: A ; STRBEN: LD A,(OLDSDATA) ;Get old data ; x x x MUTE SHFT EN DAT CLK ; Going in x L L x H AND 00000010B ;Let old data bit through OR 00000101B ;Set EN high and assure CLK bit high OUT (PIOBD),A ;..output it and make Clk low ; x x x MUTE SHFT EN DAT CLK ; Coming out x L H x H ; x x x MUTE SHFT EN DAT CLK ; Going in x L H L H AND 00000011B ;Set EN low, let data thru, leave Clk bit high OUT (PIOBD),A ;Output with Clk going high ; x x x MUTE SHFT EN DAT CLK ; Coming out x L L L H RET ;*** End: STRBEN routine ************************** ;*** Begin: SYN Freq Shift OUT subroutine ********* ; ; Input: A bit in Reg A, right justified (LSB position), RAM byte OLDSDATA. ; Output: PIO B, updated OLDSDATA. ; Action: Output the shift data bit to PIO B, update RAM byte OLDSDATA ; SYNFSOUT: RLCA ;Bit 0 to 1 0001 -> 0010 RLCA ; .. 1 to 2 0010 -> 0100 0100 -> 1000 RLCA ; .. 2 to 3 (bit 3 is "Freq Shift bit" posn) ; x x x MUTE SHFT EN DAT CLK ; Going in x x x x x AND 00001000B ;Let just the "/Freq Shift bit" through LD C,A ;Save fast access copy LD A,(OLDSDATA) ;Get old data bit logic levels OR C ;Set corresponding high bits OUT (PIOBD),A ;..output it LD (OLDSDATA),A ;Update OLD Serial DATA byte in RAM RET ;*** End: SYNFSOUT routine *********************** ; * * * * * * * Interrupt routines * * * * * * * * * ;*** Begin: CTC 0 HS Interrupt Routine ************************** ; ; At present, the CTC int routine does not work to preserve any registers. ; ; Regs used: ; A - GP ; B - GP ; C - GP ; DE - Pointer to OSW Instr Table ; HL - Various: 1) Pointer to status variables ; 2) RAM addrs for reconstructed OSW ; IX - Addrs ptr into: SET b,(HL) table ; ; Inputs: ; PIO A 01H ; Read PIO A for constructing parallel data ; Pulse outputs: -Subject to change- ; PIO A 20H ; Output notice, SYNC found and Cnt84=0 ; PIO A 10H ; Output notice, SYNC found and Cnt84/=0 ; ; Overall. Read serial data bit stream. Assemble OSW in memory. ; Service CTC with ratiometric cnt ; ; ; Operation. ; Immediately upon entry, read the logic level present in the serial ; data stream. Assemble this bit into a byte - part of 8 contigous bits in - ; order to examine for the SYNC pattern. ; ; Sync detect operation. ; ; ;OSW data word construction. ; OSW data is assembled in memory: The even Info (I) bits are are first sought ; out, then the odd I bits. The assembly in memory involves the use of a table ; in PROM that dictates A) which of the four words in RAM the bit is to be ; placed and B) what the bit position (7-0) is. ; ORG 0A00H CT0HSI: ; CTC 0 INT routine EI IN A,(PIOAD) ; Reading PIO A immediately after arriving AND 01H ; Mask off all bits except LSB LD C,A ; Fast access copy LD HL,CT0HSIVA ; Setup pointer to CTC 0 Int variables ; LD A,(INHSDATA) ; Pull in old data LD A,(HL) ; Pull in old data SLA A ; Shift the old data left OR C ; Combine with new bit saved ; LD (INHSDATA),A ; Save data (in Reg A) into RAM LD (HL),A ; Save data (in Reg A) into RAM INC HL ; Point to CNT84 and ... DEC (HL) ; Decrement Cnt84 (84 -> 0 cnt) -Flags aff- JP Z,CT0HS100 ; jump if Cnt84 reached Zero CT0HS300: ;Present program state: Cnt84 /= 0 ; LD A,C ; Get possible Sync data back into A CP 10101100B ; Compare with SYNC pattern in *Reg A* JP NZ,CT0HS900 ; To data output if no match ;Pres state; Cnt84 /= 0 and SYNC match ; LD A,10H ; ** Diagnostic aid ** ; OUT (PIOAD),A ; Output notice, /84 and SYNC found ; XOR A ; Clear Reg A ; OUT (PIOAD),A ; .. and output CT0HS301: LD A,(SYNFND) CP 1 JP Z,CT0HS900 ; If SYNC Found flag true, ignore ;Pres state; Cnt84 /= 0, SYNC match, SYNFnd=0 LD A,(SYPB84CT) INC A LD (SYPB84CT),A LD A,(RLDC84) CP 1 ; Zero FLAG is set if RLDC84 = 1 JP NZ,CT0HS900 ; Jump if flag NOT set CT0HS310: ;Pres state: Cnt84 Reload Enable flag set. LD A,84 LD (CNT84),A LD A,2 LD (SYNNPC),A XOR A LD (SYPB84CT),A LD (RLDC84),A INC A LD (SYNFND),A ; Set SYNc FounD flag LD DE,OSWIBT ; Get pntr into OSW data structure at top ; .. points to 8th Sync bit when reloaded JP CT0HS900 ; To data reconstruction ;*************************************************************** CT0HS100: ;Present cond: Cnt_84=0 ; .. points to 8th Sync bit when reloaded ; LD A,C ; Get data CP 10101100B ; Compare SYNC pattern w/data in Reg A JP NZ,CT0HS101 ; Do actions for no Sync match CT0HS102: ;Pres cond: SYNC match and cnt84=0 XOR A ; Clr Reg A LD (SYPB84CT),A ; Clr SYNC Pattern Count LD (SYNNPC),A ; Clr SYNc pattern Not Present Count INC A LD (PRVDATGD),A ; Set PreV data good flag LD (SYNFND),A ; Set SYNc FouND flag LD A,20H ; ** Diagnostic aid ** OUT (PIOAD),A ; Output notice, Cnt84=0 and SYNC found XOR A ; Clear Reg A OUT (PIOAD),A LD A,84 LD (CNT84),A ; Re-load Count 84 LD DE,OSWIBT ; Reload pointer into OSW data instr JP CT0HS900 CT0HS101: ;Present cond: Cnt_84=0 and /Sync match XOR A ; Clr LD (SYNFND),A ; Clr SYNc FouND flag LD (PRVDATGD),A ; Clr PReVious DATa Good LD A,84 ; Reload Count 84 LD (CNT84),A LD DE,OSWIBT ; Reload pointer into OSW data instr LD A,(SYPB84CT) ; Get SYNC Pattern Count CP 1 JP Z,CT0HS111 CT0HS112: XOR A ; Clr LD (SYPB84CT),A ; Clr SYNC Pattern Count LD A,2 LD (SYNNPC),A ; Reset SYNc Not Present Count JP CT0HS900 CT0HS111: ;Present condition: Sync_Pat_Cnt=1 LD A,(SYNNPC) ; Get SYNc Not Present Count DEC'd 2->0 DEC A ; SYNc Not Present Count LD (SYNNPC),A ; Replace SYNc Not Present Count JP NZ,CT0HS122 CT0HS121: ;Pres cond.: SYNNPC=0 XOR A ; Clr INC A ; Set bit in: LD (RLDC84),A ; .. Re-LoaD Count 84 flag LD A,2 LD (SYNNPC),A ; Set new SYNc Not Present Count CT0HS122: XOR A ; Clr LD (SYPB84CT),A ; Clr SYNC Pattern Count ;************************************************************** ;*** Begin: Qualify HS SYNC ABsent *********************** ; 1) Must be in CNT84 = 0 or 84, AKA SYNC period ; 2) Sample SYNFND (SYNc FouND) flag and do statistical checks on counts - ; SYNC must be absent x number of times in a row before HSSYNAB flag is ; set. ; CT0HS900: LD A,(CNT84) ; We must be in SYNC period ... CP 84 ; ..check.. JP NZ,CT0HS901 ;No..jump to exit ;Present condition: in SYNC period. LD A,(SYNFND) ; has SYNC actually been found? CP 1 JP NZ,CT0HS910 ; jump if SYNC not found ;Present state: Sync found LD A,(SYNFNDCT) ; Get: SYNc FouND CounT INC A ; Increment LD (SYNFNDCT),A ; Update: SYNc FouND CounT CP 4 ; Have we reached a count of xx? TBT766 ; CP 3 ; Have we reached a count of xx? TBT766 JP NZ,CT0HS901 ; .. jump if no .. ;Present state: Sync found, and SYNFNDCT ; .. at terminal value. XOR A ; Yes ... Clr all counts LD (SYNFNDCT),A ; Update: SYNc FouND CounT LD (SYNNFNDCT),A ; Update: SYNc Not FouND CounT ;Display output LD A,053H ;"S" - HS sync found LD (ASCDSPC0),A ; .. put into Right-most Char ; ; More program action when HS SYNC good ; INC A ; Set bit ; LD (xxx),A ; .. to set flag JP CT0HS901 ;Go to exit ... CT0HS910: ;Present state: Sync not found LD A,(SYNNFNDCT) ; SYNc Not FouND CounT INC A ; Increment LD (SYNNFNDCT),A ; Update: SYNc Not FouND CounT CP 30 ; Have we reached a count of xx? JP NZ,CT0HS901 ; .. jump if no .. ;Present state: Sync not found, and ; .. SYNc Not FouND CT at terminal value. XOR A ; Yes ... Clr all counts LD (SYNFNDCT),A ; CLR: SYNc FouND CounT LD (SYNNFNDCT),A ; CLR: SYNc Not FouND CounT ;Program action when HS SYNC not present ; ..such as setting HSSYNAB flag INC A ; Set bit LD (HSSYNAB),A ; .. then set HS SYNc ABsent flag ;Display output LD A,04EH ;"N" - No HS sync LD (ASCDSPC0),A ; .. into right-most Char CT0HS901: ;Exit label ;*** End: Qualify HS SYNC ABsent ******************** ;*** Begin: CTC 0 HS timing service **************************************** ; ** Moved to prevent conflict with PIO A interrupt service ORG 0B00H CT0HSTS: ; CTC 0 timing, ratiometric clock routine LD HL,CT0HSDNM ; Point to the count in the denominator DEC (HL) ; Implicit compare w/0 JP Z,CT0HS43 ; Counted down to zero? LD A,(HL) ; LD does not affect Flags CP 9 ; Val = numerator + 1 (was 16 for 15) JP C,CT0HS44 ; Carry bit: Val-1 or less (Ratio numerator) ; Otherwise, default to count for smaller period (43) - no denom init DI LD A,CTCLCEHS ; Cnt must follow OUT (CT0),A LD A,69 ; CTC cnt for smaller period (was 43) OUT (CT0),A EI JP CT0HSOSW ; Exit CT 0 HSTS routine ; RETI CT0HS43: ; Count for smaller per, re-init denom DI LD A,CTCLCEHS ; Cnt must follow OUT (CT0),A LD A,69 ; CTC cnt for smaller period (was 43) OUT (CT0),A LD (HL),18 ;Re-init CLK cnt (= to value of Ratio denom) EI ; Individual exits used to JP CT0HSOSW ; Exit CT 0 HSTS routine ; RETI ; save CPU T states CT0HS44: ;Count for longer period (which was 44) DI LD A,CTCLCEHS ; Cnt must follow OUT (CT0),A LD A,70 ; CTC cnt for longer period (was 44) OUT (CT0),A CT0HSEXT: ; Exit NOP EI ; JP CT0HSOSW ; Exit CT 0 HSTS routine ; RETI ;*** End: CTC 0 HS timing service ****************************** ;*** Begin: Operations select ****************** ORG 0B50H CT0HSOSW: ; Don't output data yet ; JP C0OEXT ; ** Diagnostic jump ** ; In lieu of ... LD A,(PRVDATGD) ; Examine PReVious DATa (SYNC?) GooD flag CP 1 ; ..Set? ; JP NZ,CT0HSTS ; ..No, go to CTC 0 timing services if not good JP NZ,C0HSEXIT ; ..No, exit ; ..Yes LD A,(DE) ; Fetch OSW Instr byte from table LD B,A ; Save temporary fast access copy AND 11000000B ; Look at just the left two data-type bits CP 01000000B ; Is this an Info bit? JP Z,C0OINF ; If Yes jump ... CP 11000000B ; .. or Parity bits? JP Z,C0OPAR ; If yes jump ... ; Sync Period sub-operation select ;Begin: Calc Addrs ********************* LD HL,C0SOTBL1 ; Get addrs of Sync Operations TaBLe ; Construct offset in reg pair BC LD A,B ; Get Low byte offset into table AND 00000111B ; SLA A ; Mult by 2 SLA A ; Mult by 2 again, total = 4 LD C,A ; Put into C - low byte LD B,0 ; ..into B - high byte ADD HL,BC ; Sum HL and BC into HL, ptr into JP list JP (HL) ; Go to JP routine list ;End: Calc addrs ************************ ;C0SOTBL1: ;Was: Ctc 0 Sync Operations TaBLe 1 ;*** Begin: OSW Data (Sync, Info, Parity) reconstruction ************* ; ; DE points to OSW Instruction Byte Table (IBT) ; B A fast-access copy of Byte from OSW IBT ; C Latest data-bit read on SC ; Note: Contents of B and C are both destroyed in this routine. ; ; Assignment: Reconstruct serially-received SCH info into RAM ; 1. Gen RAM addrs pntr (HL) for Info destination. ; 2. Gen ROM addrs in IX reg into C0SETTBL to execute the proper ; SET b,(HL) instr for setting a bit in the word pointed to by HL. ; ORG 0BA0H C0OINF: ;Pres state: OSW IB in B, Data = 1 or 0 LD A,C ; Get copy of latest OSW data bit AND 01H ; Mask off all bits, leave just LSB JP Z,C0OEXT ; Jump if data = 0 C0OCON: ;Pres state: Latest Info bit = 1 LD HL,OSWCST ; Get base adrs for const. words in RAM LD A,B ; Get fast access copy of OSW Instr byte AND 00000111B ; Byte sel bits: xxxx xddd, offset f/adrs ADD L ; Low byte addrs in A = Offset_A + base_L LD L,A ; Reg A into L for HL pair LD A,B ; Get our saved fast access copy of OSW IB AND 00111000B ; Data-bit-position bits: xxcc cxxx RRCA ; Rotate Rt Circular 00111000 --> 00011100 ; ..Value remaining in A is 4X bit posn LD C,A ; Low byte offset XOR A ; Clr A to.. LD B,A ; .. clr the high byte LD IX,C0SETTBL ; Get base addrs of C0 SET instr TaBLe ADD IX,BC ; Create addrs in table JP (IX) ; Go to instr C0SETTBL: ; Ctc 0 SET inst TaBLe SET 0,(HL) ; Set Bit 0 in byte @HL to a one JR C0SETRET SET 1,(HL) ; Set Bit 1 in byte @HL to a one JR C0SETRET SET 2,(HL) JR C0SETRET ; Bit 2 ... SET 3,(HL) JR C0SETRET SET 4,(HL) JR C0SETRET SET 5,(HL) JR C0SETRET SET 6,(HL) JR C0SETRET SET 7,(HL) ; JR C0SETRET ; Not necess. JR C0SETRET ORG 0C00H C0SETRET: C0OPAR: NOP C0OEXT: C0HSEXIT: DEC DE ; Update OSW Instr pntr to next (lower) addrs ; .. subject to re-loading along with Cnt84 ;*** End: OSW Data (Sync, Info, Parity) reconstruction ************** RETI ;*** End: CTC 0 HS int routine ********************************* ;*** Begin: CTC 0 LS int routine ********************************** ; ; Low-speed data Interrupt Service Routine ; Detects, synchronizes, qualifys to Low Speed (LS) Trunk data ; ORG 0C10H CT0LSI: ; CTC 0 LS INT routine ; EI ;Don't EN ints yet... IN A,(PIOAD) ; Reading PIO A immediately after arriving AND 01H ; Mask off all bits except LSB LD C,A ; Temp storage ;*** Begin: Setup CTC 1 for Disconnect data sampling *** ;*** Place in line with LS CTC Int service routine *** LD A,CTCLRELS ;Load count, Reset, Low Speed for DS detect OUT (CT1),A LD A,26 ; Approx 1/4 of full 104 cnt period OUT (CT1),A XOR A ; CLR Reg A LD (DSSEQPER),A ; CLR DISconnect SEQuence PERiod counter ;*** End: Setup CTC 1 for Disconnect data sampling *** EI ; * Req'd for CTC 1 DiS SEQ int servicing LD A,(INLSDATA) ; Pull in old data SLA A ; Shift the old data left OR C ; Combine with new bit saved LD C,A ; Save fast access copy LD (INLSDATA),A ; Save data into RAM ; JP CT0LS900 ; * Diagnostic jump * LD HL,CT0LSIVA ; Setup pointer to CTC 0 Int variables DEC (HL) ; Decrement Cnt21 (21 -> 0 cnt) JP Z,CT0LS100 ; jump if Cnt21 reached Zero CT0LS300: ;Present program state: Cnt21 /= 0 ; LD A,C ; Get possible Sync data back into A CP 01100111B ; Compare with SYNC pattern in *Reg A* JP NZ,CT0LS900 ; To data output if no match ;Pres state; Cnt21 /= 0 and SYNC match ; LD A,10H ; ** Diagnostic aid ** ; OUT (PIOAD),A ; Output notice, /21 and SYNC found ; XOR A ; Clear Reg A ; OUT (PIOAD),A ; .. and output CT0LS301: LD A,(lsSYNFND) CP 1 JP Z,CT0LS900 ; If SYNC Found flag true, ignore ;Pres state; Cnt21 /= 0, SYNC match, SYNFnd=0 LD A,(lsSYPB21C) INC A LD (lsSYPB21C),A LD A,(lsRLDC21) CP 1 ; Set Zero FLAG if =1 JP NZ,CT0LS900 ; Jump if flag NOT set CT0LS310: ;Pres state: Cnt21 Reload Enable flag set. LD A,21 LD (CNT21),A LD A,2 LD (lsSYNNPC),A XOR A LD (lsSYPB21C),A LD (lsRLDC21),A INC A LD (lsSYNFND),A ; Set SYNc FounD flag ; LD DE, ; Get pntr into OSW data structure at top ; .. points to 8th Sync bit when reloaded JP CT0LS900 ; To data reconstruction ;*************************************************************** CT0LS100: ;Present cond: Cnt_21=0 LD A,40H ; ** Diagnostic aid ** OUT (PIOAD),A ; Output notice CTC 0 LS XOR A ; Clear Reg A OUT (PIOAD),A ; .. points to 8th Sync bit when reloaded LD A,C ; Get data LD A,(INLSDATA) ; Pull in old data Ver.:TBT634 CP 01100111B ; Compare SYNC pattern w/data in Reg A JP NZ,CT0LS101 ; Do actions for no Sync match CT0LS102: ;Pres cond: SYNC match and cnt21=0 XOR A ; Clr Reg A LD (lsSYPB21C),A ; Clr SYNC Pattern Count LD (lsSYNNPC),A ; Clr SYNc pattern Not Present Count INC A LD (lsPRVDATGD),A ; Set PreV data good flag LD (lsSYNFND),A ; Set SYNc FouND flag LD A,20H ; ** Diagnostic aid ** OUT (PIOAD),A ; Output notice, Cnt21=0 and SYNC found XOR A ; Clear Reg A OUT (PIOAD),A LD A,21 LD (CNT21),A ; Re-load Count 21 ; LD DE, ; Reload pointer into OSW data instr JP CT0LS900 CT0LS101: ;Present cond: Cnt_21=0 and /Sync match XOR A ; Clr LD (lsSYNFND),A ; Clr SYNc FouND flag LD (lsPRVDATGD),A ; Clr PReVious DATa Good LD A,21 ; Reload Count 21 LD (CNT21),A ; LD DE, ; Reload pointer into OSW data instr LD A,(lsSYPB21C) ; Get SYNC Pattern Count CP 1 JP Z,CT0LS111 CT0LS112: XOR A ; Clr LD (lsSYPB21C),A ; Clr SYNC Pattern Count LD A,2 LD (lsSYNNPC),A ; Reset SYNc Not Present Count JP CT0LS900 CT0LS111: ;Present condition: Sync_Pat_Cnt=1 LD A,(lsSYNNPC) ; Get SYNc Not Present Count DEC'd 2->0 DEC A ; SYNc Not Present Count LD (lsSYNNPC),A ; Replace SYNc Not Present Count JP NZ,CT0LS122 CT0LS121: ;Pres cond.: SYNNPC=0 XOR A ; Clr INC A ; Set bit in: LD (lsRLDC21),A ; .. Re-LoaD Count 21 flag LD A,2 LD (lsSYNNPC),A ; Set new SYNc Not Present Count CT0LS122: XOR A ; Clr LD (lsSYPB21C),A ; Clr SYNC Pattern Count ;************************************************************** ;*** Begin: Qualify LS SYNC present *************************** ; 1) We must be in CNT21 = 0/21 AKA LS SYNC period ; 2) Sample lsSYNFND (low Speed SYNc FouND) flag and do statistical checks ; on counts ; CT0LS900: LD A,(CNT21) ; We must be in SYNC period ... CP 21 ; ..check.. JP NZ,CT0LS901 ;No..jump ; Yes - in SYNC period.. LD A,(lsSYNFND) ; was SYNC actually found? CP 1 JP NZ,CT0LS910 ; jump if SYNC not found ;Present state: Sync found LD A,(lsSYNFNDCT) ; Get: SYNc FouND CounT INC A ; Increment LD (lsSYNFNDCT),A ; Update: SYNc FouND CounT CP 3 ; Have we reached a count of xx? JP NZ,CT0LS901 ; .. jump if no .. ;Present state: Sync found, and SYNFNDCT ; .. at terminal value. XOR A ; Yes ... Clr all counts LD (lsSYNFNDCT),A ; .. SYNc FouND CounT LD (lsSYNNFNDCT),A ; .. SYNc Not FouND CounT ; ;Program action when LS SYNC good ; INC A ; Set bit ; LD (xxx),A ; .. to set flag JP CT0LS901 ;Go around below ... CT0LS910: LD A,(lsSYNNFNDCT) ; SYNc Not FouND CounT INC A ; Increment LD (lsSYNNFNDCT),A ; Update: SYNc Not FouND CounT CP 8 ; Have we reached a count of xx? JP NZ,CT0LS901 ; .. jump if no .. ;Present state: Sync not found, and ; .. SYN Not FouND CT at terminal value. XOR A ; Yes ... Clr all counts LD (lsSYNFNDCT),A ; Update: SYNc FouND CounT LD (lsSYNNFNDCT),A ; Update: SYNc FouND CounT ;Program action when HS SYNC not present ; such as setting LSSYNAB flag INC A ; Set bit ; LD (LSSYNAB),A ; .. to set HS SYNc ABsent flag LD (GOTOSC),A ; .. to set GOTO Setup Channel CT0LS901: ;Counts have not reached terminal values. ;*** End: Qualify LS SYNC present ******************************* ;*** Begin: CTC 0 Low Speed timing service ************************ ; ORG 0D20H CT0LSTS: ; CTC 0 timing, ratiometric clock routine LD HL,CT0LSDNM ; Point to the count in the denominator DEC (HL) ; Implicit compare w/0 JP Z,CT0LS43 ; Counted down to zero? LD A,(HL) ; LD does not affect Flags CP 4 ; Val = numerator + 1 (was 16 for 15) JP C,CT0LS44 ; Carry bit: Val-1 or less (Ratio numerator) ; Otherwise, default to count for smaller period (43) - no denom init DI LD A,CTCLCELS ; Cnt must follow OUT (CT0),A LD A,104 ; CTC cnt for smaller period (was 43) OUT (CT0),A EI RETI CT0LS43: ; Count for smaller per, re-init denom DI LD A,CTCLCELS ; Cnt must follow OUT (CT0),A LD A,104 ; CTC cnt for smaller period (was 43) OUT (CT0),A LD (HL),18 ;Re-init CLK cnt (= to value of Ratio denom) EI ; Individual exits used to RETI ; save CPU T states CT0LS44: ;Count for longer period (which was 44) DI LD A,CTCLCELS ; Cnt must follow OUT (CT0),A LD A,105 ; CTC cnt for longer period (was 44) OUT (CT0),A CT0LSEXT: ; Exit NOP EI RETI ;*** End: CTC 0 Low Speed timing service ***************************** ;*** End: CTC 0 int routine ****************************************** ;*** Begin: Ctc 1 DISconnect INT routine ********************* ; ; This routine performs identification of the 8-bit Disconnect Sequence. ; Sampling of the incoming Low Speed data is effectively performed at ; twice the rate normally used for LS data sampling as well as being ; shifted in time in order to sample the DiS SEQ mid-bit. ; ; DSSEQPER - DiSconnect SEQuence PERiod: Determines when sampling ; is performed. ; Normally cleared in routine enabling ints allowing this ; routine to be called. ; Range: coming in 0-2, incremented in routine to yield 1-3 ; DSDATA - DiSconnect DATA: read in, shifted during sampling ; ; DSSEQFLAG - DiSconnect SEQuence FLAG, set when disconnect found ORG 0D60H CT1DISINT: ; CTC 1 DISconnect INTerrupt PUSH AF LD A,(DSSEQPER) ; Get DISconnect TiMing PERiod cnt INC A ; Incr LD (DSSEQPER),A ; Put back (Cleared by LS Int routine) CP 1 ; Determine the period are we in .. JP Z,CT1DS101 ; .. 1st period CP 3 JP Z,CT1DS101 ; .. 3rd period CT1DS100: ; Period 2, simply return. POP AF EI ; Enable Int RETI ; ***Exit*** CT1DS101: ; Periods 1 or 3, sample data. PUSH BC ; *** LD A,(DSSEQBITCT) ; DiS SEQ BIT CounT -- Used in determining INC A ; Increment count -- contiguous Disconnect LD (DSSEQBITCT),A ; Restore -- Sequence patterns ; *** IN A,(PIOAD) ; Read PIO A AND 1 ; Mask off all except LSB LD B,A ; Save bit temporarily LD A,(DSDATA) ; Pull in old data Disconnect data SLA A ; Shift the old data left OR B ; Combine with new bit saved LD (DSDATA),A ; Put data back CP 10101100B ; Compare with Disconnect data JP NZ,CT1DS800 ; Jump if no match ;Pgm state: Disconnect data match, ; .. periods 1 or 3 ; XOR A ; Clear Reg A ** Enable this code if req'd ** ; LD (DSSEQLSPER),A ; CLR DiSconnect SEQuence Low Speed PERiod ; INC A ; LD (DSSEQFLAG),A ; Set flag when Disconnect Sequence is found LD A,(DSSEQBITCT) ; Get BIT CounT LD B,A ; Fast access copy LD (DSSEQOLDBC),A ; Save as OLD Bit Count XOR A LD (DSSEQBITCT),A ; CLR BIT Count LD A,B ; Get old bit count CP 8 JP NZ,CT1DS700 CT1DS600: LD A,(DSSEQCONCT) ; Incr count of CONtiguous CounT INC A LD (DSSEQCONCT),A XOR A INC A ;I think this is needed ... LD (DSSEQCONTG),A ; Set flag: CONTiGuous ; INC A LD (GOTOSC),A ; Set flag ; **** Begin Diagnostic aid **** LD A,10H ; ** Diagnostic aid ** OUT (PIOAD),A ; Output notice, Disconnect found XOR A ; Clear Reg A OUT (PIOAD),A ; reset bit ; **** End Diagnostic aid **** JP CT1DS800 ; Jump over code CT1DS700: XOR A LD (DSSEQCONTG),A ; ClR flag LD (DSSEQCONCT),A ; .. count CT1DS800: ;Pgm state: /Dis seq data match, period 1 or 3 ; ... or: Dis seq data match, period 1 or 3 LD A,(DSSEQPER) ; Get DISconnect TiMing PERiod CP 3 ; Check period .. JP NZ,CT1DS900 ; .. 1st period, jump ... ; 3rd period .. LD A,CTCRS ; Reset CTC 1 - no more CTC 1 ints OUT (CT1),A ; Output it CT1DS900: ; 1st period - also used by 3rd to exit POP AF POP BC EI ; RETI ; ***Exit*** ;** End: CTC 1 Disconnect int routine ********************* ;** Begin: PIO A HS Interrupt Routine *********************************** ; The PIO routine triggers on the positive edge and reads the count in ; CTC 0. ; Alt Regs: ; A - GP ; B - # of edges sampled (cnt within PIO INT routine) ; C - Tally of clk counts read from CTC ; ORG 0DE0H PIOAHSIR: ; JP PIOBIR ; * Diagnostic jump * EX AF,AF' ; Save AF pair EXX ; Swap: BC, DE, HL ; The following input occurs 18 to 22 uS after pos xsition on ; PIO A.0. The avg appears to be about 20 uS, with random occurances ; out to 35 uS. IN A,(CT0) ; Read count from CTC 0 ; SRA A ; divide by two ADD C ; Sum clk cnt into ACC LD C,A ; and save again. DEC B ; inspect number of times thru loop JP Z,PIOIN1 ; DEC'd to zero EXX EX AF,AF' EI RETI ; Exit 1 PIOIN1: SRA C ; Tot divide: two SRA C ; four LD A,C CP 30 ; Nominal 12 (unequalized) ; CP 26 ; Nominal 12 (unequalized) JP C,PIOIN2 ; LT: ACCUM < Lo_cnt (Carry bit set) CP 32 ; Nominal 14 (unequalized) ; CP 30 ; Nominal 14 (unequalized) JP C,PIOIN3 ; EQ, ie: Lo_cnt < ACC < HI_cnt then jmp ; GT: Hi_cnt < ACCUM LD A,CTCLCEHS ; Input new period count OUT (CT0),A ; LD A,69 ;Load the shorter count (was 43) LD A,68 ;Load the shorter count (was 43) OUT (CT0),A XOR A LD C,A ; Clr period cnt LD B,4 ; Reset count EXX EX AF,AF' EI RETI ; Exit 2 PIOIN2: LD A,CTCLCEHS ; Input new period count OUT (CT0),A ; LD A,70 ; Load the longer count (was 44) LD A,71 ; Load the longer count (was 44) OUT (CT0),A PIOIN3: ; No adjustment to clock count XOR A LD C,A ; Clr period cnt LD B,4 ; Reset count EXX EX AF,AF' EI RETI ; Exit 3 PIOBIR: EXX EX AF,AF' EI RETI ; Exit ;*** End: HS PIO int routine ******************** ;*** Begin: PIO A LS Interrupt Routine *********************************** ; The PIO routine triggers on the positive edge and reads the count in ; CTC 0. ; Alt Regs: ; A - GP ; B - # of edges sampled (cnt within PIO INT routine) ; C - Tally of clk counts read from CTC ; ORG 0E30H PIOALSIR: ; JP PIOLSBIR ; * Diagnostic jump * EX AF,AF' ; Save AF pair EXX ; Swap: BC, DE, HL IN A,(CT0) ; Read count from CTC 0 ; Delay .. NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP SRA A ; divide by two LD D,A ; .. and save. IN A,(PIOAD) ; Read PIO A again - make sure we have ; .. transitioned to a high state - weeding ; .. out any negative transitions so we can ; .. phase lock to the Disconnect Sequence ; .. as well as data. AND 1 ; Mask off all exc LSB and compare ACC w/0 JP Z,PIOLS4 ; If ACC=0, exit (we don't want neg transitions) LD A,D ; Get saved and divided count is we passed ; the '1' test on PIO A ADD C ; Sum clk cnt into ACC LD C,A ; and save again. ; IN A,(CT0) ; Read count from CTC 0 ; SRA A ; divide by two ; ADD C ; Sum clk cnt into ACC ; LD C,A ; and save again. DEC B ; inspect number of times thru loop JP Z,PIOLS1 ; DEC'd to zero EXX EX AF,AF' EI RETI ; ** Exit 1 ** PIOLS1: ; SRA C ; Tot divide: two SRA C ; four LD A,C CP 45 ; Nominal 12 JP C,PIOLS2 ; LT: ACCUM < Lo_cnt (Carry bit set) CP 55 ; Nominal 14 JP C,PIOLS3 ; EQ, ie: Lo_cnt < ACC < HI_cnt then jmp ; GT: Hi_cnt < ACCUM LD A,CTCLCELS ; Input new period count OUT (CT0),A LD A,94 ;Load the shorter count (was 43) OUT (CT0),A XOR A LD C,A ; Clr period cnt LD B,4 ; Reset count EXX EX AF,AF' EI RETI ; ** Exit 2 ** PIOLS2: LD A,CTCLCELS ; Input new period count OUT (CT0),A LD A,114 ;Load the longer count (was 44) OUT (CT0),A PIOLS3: ;No adjustment to clock count XOR A LD C,A ; Clr period cnt LD B,4 ; Reset count ; .. use exit below PIOLS4: ;Exit 4 - Arrive here on false PIO edge trigger ;.. due to noise on neg edge of waveform EXX EX AF,AF' EI RETI ; Exit 3 and 4 PIOLSBIR: EI RETI ; Exit ;*** End: LS PIO int routine ******************** ORG RAMSTR ;Begin at 1st RAM addrs, 7FFH is top address ;CTC 0 HS int vars CT0HSIVA: INHSDATA: DEFB 0 ;Incoming data (bits shifted left) CNT84: DEFB 0 ;Cnt84: Counts 84 -> 0 CT0HSDNM: DEFB 0 ;Denominator count (circular) ORG RAMSTR + 010H ;CTC 0 Low Speed (LS) int vars CT0LSIVA: CNT21: DEFB 0 ;Cnt21: Counts 21 -> 0 CT0LSDNM: DEFB 0 ;Denominator count (circular) INLSDATA: DEFB 0 ;Incoming low speed data (bits shifted left) ORG RAMSTR + 020H ; CTC 1 Disconnect int vars DSDATA: DEFB 0 ; Parallel constructed DiSconnect DATA byte DSSEQPER: DEFB 0 ; DiSconnect SEQuence PERiod DSSEQBITCT: DEFB 0 ; DiSconnect SEQuence BIT CounT DSSEQOLDBC: DEFB 0 ; DiSconnect SEQuence OLD Bit Count DSSEQCONCT: DEFB 0 ; DiSconnect SEQuence CONtiguous CounT DSSEQCONTG: DEFB 0 ; DiSconnect SEQuence CONTiGuous flag ORG RAMSTR + 030H INTVTB: ; ***** INT Vector TaBle ***** ; One of the two addresses occupy the CT0IV variable: ; CT0LSI - CTC 0 int routine vector Low Speed ; CT0HSI - CTC 0 int routine vector High Speed ; CT0IV: DEFW 0 CT1IV: DEFW 0 CT2IV: DEFW 0 CT3IV: DEFW 0 PIOAIV: DEFW 0 ORG RAMSTR + 050H OSWCST: ;Base adrs for OSW ConSTruction ORG RAMSTR + 0060H SYNFND: DEFB 0 ;SYNc FouND flag RLDC84: DEFB 0 ;Re-LoaD Count 84 flag SYNNPC: DEFB 0 ;SYNC Not Present Count DEC'd 3->0 SYPB84CT: DEFB 0 ;SYnc Patterns Between 84 rollover CounT PRVDATGD: DEFB 0 ;PReVious DATa GooD SYNFNDCT: DEFB 0 ;SYNc FouND CounT SYNNFNDCT: DEFB 0 ;SYNc Not FouND CounT HSSYNAB: DEFB 0 ;HS SYNc ABsent flag ORG RAMSTR + 0070H lsSYNFND: DEFB 0 ;SYNc FouND flag lsRLDC21: DEFB 0 ;Re-LoaD Count 21 flag lsSYNNPC: DEFB 0 ;SYNC Not Present Count DEC'd 3->0 lsSYPB21C: DEFB 0 ;LS SYnc Patterns Between 21 rollover Count lsPRVDATGD: DEFB 0 ;PReVious DATa GooD lsSYNFNDCT : DEFB 0 ;ls SYNc FouND CounT lsSYNNFNDCT: DEFB 0 ;ls SYNc Not FouND CounT ORG RAMSTR + 0080H ;Base adrs for OSW output OSWXOUT: ; +0 A0 - A7 Left half "Address" byte ; +1 A8 - A15 Right half "Address" ; +2 0 0 0 T 0 0 C0 C1 Type, Left 2 Data/Freq MSB's ; +3 C2 - C9 Data/Freq, right eight bits ; Freq shft bit TBT774 ORG RAMSTR + 0090H ;Base adrs for OSW Screened output OSWSOUT: ; +0 A0 - A7 Left half "Address" byte ; +1 A8 - A15 Right half "Address" ; +2 0 0 0 T 0 0 C0 C1 Type, Left 2 Data/Freq MSB's ; +3 C2 - C9 Data/Freq, right eight bits ORG RAMSTR + 00A0H OLDSDATA: DEFB 0 ;OLD Serial DATA - from previous output SYNFREQL: DEFB 0 ;Least significant byte SYNFREQH: DEFB 0 ;Most significant byte ZRQSHFT0: DEFB 0 ; STCHFPTR: DEFB 0 ;SeTup CHannel Frequency PoinTeR 0,1 ... X ; ... doubled in subroutine ORG RAMSTR + 00B0H ; * Note: Cannot unless HS Int routine changed GOTOSC: DEFB 0 ;GOTO Setup Channel, accessed by LS Int GOTOVC: DEFB 0 ;GOTO Voice Channel, accessed by HS Int ORG RAMSTR + 00C0H INCCNT: ORG RAMSTR + 00D0H ;Diagnostic output block - viewable w/Log Ana DIAG00: DEFB 0 DIAG01: DEFB 0 DIAG02: DEFB 0 DIAG03: DEFB 0 DIAG04: DEFB 0 DIAG05: DEFB 0 ;TRAKMD1: DEFB 0 ;TRAK MODE 1 flag ORG RAMSTR + 00E0H ;Diagnostic output block - viewable w/Log Ana PIOASSD: DEFB 0 ;PIO A Syn Serial Data PIOASEB: DEFB 0 ;PIO A Syn "ENable" bit ORG RAMSTR + 00F0H ; ; ;SYNthesizer Read Data Ref or N SYNRDRN: DEFB 0 ;Data type bit, "R"ef or "N" SYNRD0: DEFB 0 ;Assembled 16 bits data, Low byte SYNRD1: DEFB 0 ; ... high byte ORG RAMSTR + 0100H ; SYNRDREF0: DEFB 0 ;Ref divisor, low byte SYNRDREF1: DEFB 0 ; ... high byte ORG RAMSTR + 0110H ; SYNRDSHFT: DEFB 0 ;Shift byte ORG RAMSTR + 0120H ; SYNRDNDV0: DEFB 0 ;N divisor, low byte SYNRDNDV1: DEFB 0 ; ... high byte ORG RAMSTR + 0130H ; DSYNRDRN: DEFB 0 ;Data type bit, "R"ef or "N" DSYNRD0: DEFB 0 ;Assembled 16 bits data, Low byte DSYNRD1: DEFB 0 ; ... high byte ORG RAMSTR + 0140H ; MDSWDAT0: DEFB 0 ;Mode switch data: "-->" "ENT" "<--" "MODE" MDSWDAT1: DEFB 0 ;Data xferred from ..DAT2 when switch closure goes ; ..away ORG RAMSTR + 0150H ; Cannot change - written to by upper EPROM C0HSSWDT: DEFB 0 ;HS Sync Switch DATa - Clr before entering HS Sync ORG RAMSTR + 0160H ; ReaD Synth data Freq PoinTeR RDSFPTR: DEFB 0 SYNDNEW: DEFB 0 ;SYN Data NEW flag ;** Begin: ******************************* ; ORG RAMSTR + 0170H ; STCHFPMX: DEFB 0 ;SeTup CHannel Freq Pointer ToP allowable ORG RAMSTR + 0180H ; SYNFSHFT: DEFB 0 ;/SYN Freq SHiFT data bit 5/12.5 KHz down ORG RAMSTR + 0190H ; DATAEBUFP: DEFB 0 ;Data enter buffer pointer ;DATAECHRP: DEFB 0 ;Data enter char pointer ORG RAMSTR + 0200H ; DATAEBUF: ;Data enter buffer DEFB 0 ;MSB DEFB 0 DEFB 0 DEFB 0 ;LSB ORG RAMSTR + 0210H ; MODEPTR: ;.. Mode PoinTeR DEFB 0 MODEPTRX6: ;.. X 5 Mode PoinTeR DEFB 0 MODETTL: DEFW 0 ORG RAMSTR + 0220H ; Setup Channel Frequency list FRQDATGD: ;FReQ DATa GooD flag ORG RAMSTR + 0240H ; Setup Channel Frequency list STCHFRQLRA: SYNBASEL: DEFB 000H ;SYN BASE Low - low byte SYNBASEH: DEFB 000H ; " - high byte SYNFSHFTRA: DEFB 0 ;/SYN Freq SHiFT data bit 5/12.5 KHz down DEFB 0 ;Spare DEFB 0D6H ;Ch 1 - low byte DEFB 000H ; .. - high byte DEFB 0 ;/SYN Freq SHiFT data bit 5/12.5 KHz down DEFB 0 ;Spare DEFB 0FEH ;Ch 2 - low byte DEFB 000H ; .. - high byte DEFB 0 ;/SYN Freq Shift data bit DEFB 0 ;Spare DEFB 026H ;Ch 3 DEFB 001H DEFB 0 ;/SYN Freq Shift data bit DEFB 0 ;Spare ; ... ; ORG RAMSTR + 0xxCH ;ReaD Synth data Freq PoinTeR DEFB 076H ;Ch 20 DEFB 001H DEFB 0 ;/SYN Freq Shift data bit DEFB 0 ;Spare ORG RAMSTR + 0270H ; CGLISTRH: ;Call Group LIST Right (LS) Half ;Search starts from bottom ORG RAMSTR + 0280H ; CGLISTLH: ;Call Group LIST Left (MS) Half ;Search starts from top ORG RAMSTR + 0290H ; CGLISTCHL: ;Call Group LIST CHanneL ORG RAMSTR + 0290H + 4*16 ; May use memory starting here CGRPCHPTR: ;Call GRouP CHan PoinTeR DEFB 0 INCCGRPCHRPC: ;Get count DEFB 0 BUF3BLNK: DEFB 0 DEFB 0 DEFB 0 DEFB 0 CGDATAPIFLG: DEFB 0 ;** End: *******************************